feat(submit): pack design + pins.lock + manifest into a single bundle.zip#165
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feat(submit): pack design + pins.lock + manifest into a single bundle.zip#165
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The submit endpoint receives one multipart 'bundle' part instead of
separate 'rtlil' and 'config' parts. Inside the zip:
manifest.json {"version": "1", "rtlil": "...", "config": "pins.lock"}
<rtlil basename> e.g. top.il, taken from rtlil_path
pins.lock the pinlock JSON
The manifest is the only contract; consumers locate the rtlil and
config payloads through it. This lays the groundwork for adding macro
folders later by extending the manifest, with no further wire-format
change.
Adds the chipflow.toml [chipflow] project_name to manifest.json under a "project" key so the backend can identify the design without parsing the config payload (useful for log lines, working-directory naming, and dashboards).
Drops the artifact next to amaranth's build output (Path(rtlil_path).parent) instead of the current working directory, so it lands inside the project's build folder alongside the rtlil it was packed from.
The key now matches what the value actually points to (pins.lock). Leaves room for adding other config-like files later without overloading a generic "config" key.
Renames manifest keys whose value names a file in the archive:
"rtlil" -> "rtlil_file", "pins_lock" -> "pins_lock_file". Plain value
keys ("version", "project") stay as-is. Makes the role of each key
self-documenting and unambiguous as the manifest grows.
The manifest key now describes the role (the design's intermediate representation) rather than the format. Lets the same key carry rtlil today and another intermediate (Verilog, FIRRTL) tomorrow without another rename. The function still takes an rtlil_path parameter because that's what the caller actually has on hand from amaranth.
Adds chipflow.toml [chipflow.silicon] process value (e.g. "sky130", "gf180") under a "process" key in manifest.json. The backend uses it to pick the right PDK / flow without re-parsing the pinlock. The pre-existing browser-prompt tests grew a real silicon.process.value on their config mock to satisfy the new attribute access.
Adds chipflow.toml [chipflow.silicon] package value (e.g. "cf20") under a "package" key in manifest.json. Together with "process", lets the backend pick the right PDK + package combination without re-parsing the pinlock.
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This was referenced Apr 30, 2026
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Summary
rtlil+configmultipart submit with a singlebundlepart carryingbundle.zip. Inside the zip:manifest.json— the only contract; consumers locate payloads through it.<design basename>— e.g.top.il, taken fromrtlil_path.pins.lock— the pinlock JSON (pinlock.model_dump_json).version: "1",project(from[chipflow] project_name),processandpackage(from[chipflow.silicon]),design_fileandpins_lock_file(zip-relative paths). Keys whose value names a file inside the archive carry a_filesuffix.bundle.zipnext to the rtlil (Path(rtlil_path).parent), so it lands inside amaranth's build folder rather than the user's CWD.Why a single bundle
One uniform shape on the wire, on disk, and in storage. The manifest is the indirection point — adding macro folders later (rebased PR #163) is purely additive: new
_filekeys + new folders, no wire-format change. Reproducibility win too: the bundle is a single self-describing artifact you can replay months later.Files
chipflow/platform/silicon_step.py—+_build_bundle_ziphelper; rewritten dry-run + submit blocks.tests/test_silicon_submit.py— kept the 3 browser-prompt tests (mocking the helper); addedTestBuildBundleZip(manifest shape, real-filename preservation) andTestSiliconSubmitBundlePost(asserts the multipart payload is{"bundle": ("bundle.zip", bytes, "application/zip")}).Cross-repo PRs
End-to-end validation
Real submission against
chipflow-api-stagingwith backend imagebranch-feat-bundle-zip-submit: build0620ceda-c829-4142-94c3-42f8abe9c518ran the full IHP SG13G2 synth + P&R flow tostatus="completed".Test plan
pytest --ignore=tests/test_cli_integration.py— 65 passed, 10 skipped (pre-existing CLI-integration skips).ruff checkclean onchipflow/andtests/.