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feat(packaging): add BlockPackageDef for hard-macro builds#167

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feat/block-package
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feat(packaging): add BlockPackageDef for hard-macro builds#167
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feat/block-package

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Summary

Adds a parameterized package type used when chipflow.toml declares package = "block". Structurally a sibling of BareDiePackageDef — pins on four sides addressed by (Side, index) — but for hard-macro targets rather than packaged chips.

Differences vs chip packages

  • No bringup pins. Blocks take power via straps from the parent and route clocks/resets through regular pins. allocate_pins() skips the chip-package bringup step (the _allocate_bringup call that reserves clock/reset/power/JTAG slots at fixed positions).
  • Parameterized per project. width/height aren't fixed values in PACKAGE_DEFINITIONS — they come from a new [chipflow.silicon.block] table. The resolver in lock_pins() constructs a BlockPackageDef instance from config when package = "block".

chipflow.toml shape

[chipflow.silicon]
process = "ihp_sg13g2"
package = "block"

[chipflow.silicon.block]
width  = 50    # pin slots on N and S edges
height = 80    # pin slots on W and E edges

width and height are pin-slot counts, same units as QuadPackageDef.width/.heightnot microns. Translation to physical dimensions happens at the backend using the process's pin pitch.

What stays the same

  • Bundle.zip / manifest.json transport — no change.
  • Lockfile shape — BlockPackageDef is added to the PackageDef discriminated union; lockfile serialization works unchanged.
  • chipflow-api / chipflow-backend wire format — unchanged.

What's left for the backend

Backend grows a "block mode" code path: detect package_type == "BlockPackageDef" from the lockfile, run the ORFS macro flow (different floorplan + PnR strategy from chip flow), output LEF / Liberty / GDS / Verilog stub. None of that is in this PR.

Test plan

  • pytest --ignore=tests/test_cli_integration.py — 69 passed, 10 skipped.
  • ruff check chipflow/ tests/ clean.
  • New tests/test_block_package.py covers: perimeter slot count, no bringup reservation, abstract bringup property raises (so accidental calls fail loud), pydantic round-trip.
  • End-to-end against staging once the chipflow-backend macro flow is in place.

Related

This PR is independent of #163 — they touch disjoint files.

Adds a parameterized package type used when chipflow.toml declares
`package = "block"`. Structurally a sibling of BareDiePackageDef — pins
on four sides addressed by (Side, index) — but for hard-macro targets
rather than packaged chips.

Differences vs chip packages:
- No I/O pad ring, no JTAG, no fixed clock/reset/power slots. Blocks
  take power via straps from the parent and route clocks/resets through
  regular pins. allocate_pins() skips the bringup-pins step entirely.
- width/height are user-defined per project rather than pulled from a
  fixed PACKAGE_DEFINITIONS entry, sourced from a new
  [chipflow.silicon.block] table:

    [chipflow.silicon]
    process = "ihp_sg13g2"
    package = "block"

    [chipflow.silicon.block]
    width  = 50
    height = 80

  width/height are pin-slot counts, same units as QuadPackageDef. The
  backend translates to physical microns using the process's pin pitch.

The lockfile flows through the existing bundle.zip pipeline unchanged —
package_type discriminator routes deserialization, and the `_file`-keyed
manifest contract on the receiving side already covers everything.
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Tests Skipped Failures Errors Time
90 10 💤 0 ❌ 0 🔥 35.822s ⏱️

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