feat(rtl): add load_blackbox_wrapper for NDA hard macros#163
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feat(rtl): add load_blackbox_wrapper for NDA hard macros#163
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Adds a tool-agnostic path for integrating hard macros (NDA SRAMs, vendor IP, PLLs) into a ChipFlow design via a `*.blackbox.json` produced by the sibling `macrostrip` tool. Macros are declared by logical name under `[chipflow.silicon.macros]` and instantiated from Python with `load_blackbox_wrapper(name, clocks=..., resets=...)`, which synthesizes an `ExternalWrapConfig` from the JSON's pin list and returns a `BlackboxWrapper` (subclass of `RTLWrapper`). At submit time the platform bundles each macro's companion files (LEF, Liberty, frame-view or real GDS, Verilog stub, blackbox JSON) into a `macros.tar.gz` with a root `manifest.json` and posts it as a third multipart field alongside `rtlil` and `config`, so the ORFS-based backend can ingest them via `ADDITIONAL_LEFS` / `ADDITIONAL_LIBS` / `ADDITIONAL_GDS_FILES` without the real macro layout ever leaving customer premises. Also widens `RTLWrapper._validate_signal_bindings` to accept either the `i_<name>` / `o_<name>` or bare `<name>` port-declaration conventions — LEF-derived hard-macro stubs use the bare form.
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Summary
load_blackbox_wrapper(logical_name, clocks=..., resets=...)loads a hard macro declared under[chipflow.silicon.macros]from a*.blackbox.jsonproduced by macrostrip, and returns aBlackboxWrapper(subclass ofRTLWrapper) ready to drop into a design.SiliconPlatform.add_macro()registers each instantiated macro with the platform.bundle.zip(not as a separate field). Each macro's companion files (LEF, Liberty, frame/real GDS, Verilog stub, blackbox JSON) live undermacros/<logical_name>/and surface inmanifest.jsonas a dict keyed by logical name with_file-suffixed paths so the chipflow-backend's existing recursive_bundle_files_from_manifestextractor picks them up — purely additive on the receiving side.RTLWrapper._validate_signal_bindingsnow accepts eitheri_<name>/o_<name>or bare<name>Verilog port-declaration conventions (LEF-derived hard-macro stubs use the bare form).[chipflow.silicon.macros]section inchipflow-toml-guide.rst;rtl-wrapper.rstgains NDA + non-NDA workflow subsections;CLAUDE.mdreflects the new config section andchipflow/rtl/surface.The same path covers non-NDA macros: run
macrostrip blackbox --frame-gds=<real.gds>instead ofmacrostrip frame, and skipmacrostrip swapon return — chipflow-lib treatsframe_gdsas "the GDS to include," frame-view or real.Manifest shape (added on top of the existing bundle keys)
{ "version": "1", "project": "...", "process": "...", "package": "...", "design_file": "top.il", "pins_lock_file": "pins.lock", "macros": { "sram_64x64": { "name": "sram_64x64", "lef_file": "macros/sram_64x64/sram_64x64.lef", "liberty_file": "macros/sram_64x64/sram_64x64.lib", "frame_gds_file": "macros/sram_64x64/sram_64x64.gds", "verilog_stub_file": "macros/sram_64x64/sram_64x64.v", "blackbox_json_file": "macros/sram_64x64/sram_64x64.blackbox.json" } } }No wire-format change vs the bundle PRs already in production: API still receives one
bundlemultipart part, backend extracts every_file-suffixed manifest leaf into the working dir.Why a single bundle (recap)
The earlier iteration of this PR posted a separate
macros.tar.gzas a third multipart field. That was reworked to use the bundle approach instead — see the merged transport work for context:Adding macros becomes additive: new manifest keys + new folders inside the same zip. No changes needed in chipflow-api or chipflow-backend.
Test plan
pytest --ignore=tests/test_cli_integration.py— 73 passed, 10 skipped (pre-existing CLI-integration skips).ruff checkclean onchipflow/andtests/.tests/test_blackbox_wrapper.py::BuildBundleWithMacrosTestCasecovers: macros omitted when none registered; macros present produce dict-keyed manifest entries with_file-suffixed paths undermacros/<logical_name>/....chipflow-api-stagingonce a real macro is wired into chipflow-test-socs.