[Raiden Weight Sync 3/7] MoE 128-lane layout and padding for TPU GMM kernels

[YixuanWang-99]

Overview

Part of the stacked Raiden weight-sync enablement PR chain replacing #5089.
Pairs with Tunix [T5] (google/tunix).

Stack:

• [M7] [Raiden Weight Sync 1/7] Add cross-repo drift guard and FFI resolution tests #5166: Cross-repo drift guard
• [M1] [Raiden Weight Sync 2/7] Support inhomogeneous layer cycle interval in raiden_unscan #5167: Inhomogeneous layer cycle support in raiden_unscan
• [M2] AI-Hypercomputer/maxtext (this PR): MoE 128-lane layout and padding (pairs with Tunix T5)
• [M3] AI-Hypercomputer/maxtext: Target-free streaming weight conversion
• [M5] AI-Hypercomputer/maxtext: Shared expert gate weight_dtype fix
• [M4] AI-Hypercomputer/maxtext: TrainingEngine Raiden FFI integration (pairs with Tunix T2a)
• [M6] AI-Hypercomputer/maxtext: Rollout cleanup

Details

• Implements 128-lane interleaving and padding in convert_utils.py to match TPU GMM kernel requirements (gmm_v2.py).
• Adds compute_padded_moe_mlp_dim in convert_utils.py.
• Adds unit tests in tests/post_training/unit/convert_utils_test.py.

Verification

• pytest tests/post_training/unit/convert_utils_test.py (6/6 passed).

Checklist

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[gemini-code-assist]

Code Review

This pull request introduces MoE padding utilities, unit tests, and compatibility shims for Tunix/tpu-inference weight sync, alongside refactoring convert_utils.py and qwen35_moe.py to support TPU GMM_v2 kernel alignment. Feedback focuses on preventing potential crashes on non-glibc systems when loading libc, avoiding abstract ShapeDtypeStruct returns when concrete arrays are present, optimizing padding logic to reduce memory overhead, validating head divisibility, and properly handling negative scan_axis indices in bounds checks.

[codecov]

Codecov Report

❌ Patch coverage is 56.66667% with 26 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
src/maxtext/integration/vllm/convert_utils.py	54.38%	17 Missing and 9 partials ⚠️

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