balar: add cached Doorbell driver and integration contracts

[nab880]

The existing direct-memory trace driver does not exercise cached packet writes followed by flushes and an MMIO doorbell. Add DoorbellTestCPU, its coherent memory topology, and focused integration contracts.

The driver issues cache-line-bounded requests, reassembles return packets, reserves payload storage beyond both packet layouts, and verifies D2H bytes by reading simulated destination memory. This layer works with the existing MMIO implementation; it does not require the optional compact protocol or retained simulator-side D2H buffers.

Validation:

• Production Doorbell code compiled from this layer against real SST cache/memory components with a mock GPU endpoint matching base MMIO's null SST D2H return pointers.
• Six cases passed: aligned and unaligned 513-byte and 4 KiB transfers, plus detected destination-memory corruption at both sizes.
• Full GPGPU-Sim integration was not run locally.
• git diff --check passed.

Incremental review PR in the contributor fork, based on balar-2-test-support. Upstream branch protection prevents feature-branch bases there. After the preceding layer lands upstream, submit this branch against sstsimulator/sst-elements:devel; retain this fork PR as its incremental review record.

Stack (review order):

1. balar-1-wire-header
2. balar-2-test-support
3. balar-3-doorbell-driver
4. balar-4-compact-mmio