fix(mmu): terminate Wishbone errors as failed accesses

[murdoa]

RiverMmu only handles Wishbone ACK responses. An ERR-only response leaves the bus and its requesting port waiting indefinitely; ACK+ERR is treated as success.

This adds an optional ERR input, tied low for existing callers. An error completes only the owning fetch/data request with done=1, valid=0, leaving page/guest-page fault flags clear. It also drops CYC/STB, abandons any active page-table or A/D-update work, and invalidates cached translations before retry. ERR takes priority if ACK is also asserted.

Tests

40 new cases cover RV32/RV64 bare accesses, Sv39 fetch/load/store faults during PTE reads, A/D writes and translated accesses, plus G-stage PTE errors. They check response ownership, idle ERR rejection and successful recovery.

All 40 pass, along with 16 existing MMU tests. On baseline, the new cases all fail and the existing cases pass. The only baseline test adaptation is an ignored wbErr constructor argument so the older API can run the same tests. Analysis, formatting and diff checks pass.

Scope

This is the MMU prerequisite, not end-to-end core access-fault support. Wiring core ERR and carrying fault classification through caches and queued frontends are separate follow-ups. Harbor's cache-classification support is already merged in Harbor PR #8. No dependency, board or README changes are included; no synthesis or hardware validation was performed.