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fix(core): propagate in-order Wishbone access faults - #9
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RossComputerGuy merged 2 commits intoOct 6, 2026
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Carry page/access classification through cache responses and fetch retirement, and report precise in-order fetch/load/store and atomic faults. Preserve destinations on failed AMO writes and prevent microcoded SC from restarting after a terminal fault. Keep OoO ERR handling unchanged until fault addresses and precise store-queue retirement are implemented.
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Depends on #8; updates Harbor to include LilithSemi/harbor#8.
Propagate Wishbone ERR through the in-order core, caches and fetch/execute path as instruction/load/store access faults rather than hangs or page faults. Retain classification with cached/fetched responses. Both AMO halves report store/AMO faults; failed AMO/SC operations preserve their destination registers.
Scope: static and microcoded in-order execution, cached and uncached. OoO deliberately retains its existing ERR-ignored behavior: precise support needs ROB fault addresses, queued fetch metadata and store-queue retirement changes. No configurations are disabled. The separate pipelined fetch interface and straddling-instruction TVAL correction are not included.
Tests: 140 new RV32/RV64 cases pass, covering ERR-only/ACK+ERR, cache refill failures, page-table access errors, page-fault controls, atomics, trap CSRs and recovery. Targeted comparison: 166 pass / 119 fail → 284 pass / 1 fail, with no lost passes. The remaining failure is identical on both: the existing dual-issue macro paging test reports that translation never became live.