RISC-V RVV cross-compilation build

Workflow runs for RISC-V RVV cross-compilation build

• Fix AVX-512 reduce_max/reduce_min missing bytes 32-39 for 8-bit types

  completed successfully:
  RISC-V RVV cross-compilation build#3328:Commitebe9991pushedbyDiamonDinoia
  master

  Oct 23, 202641m 29s
  More actions for workflow run 3328

• Fix AVX-512 reduce_max/reduce_min missing bytes 32-39 for 8-bit types

  completed successfully:
  RISC-V RVV cross-compilation build#3327:Pull request#1431openedbyemrys53
  emrys53:bug/reduce_min/max

  Oct 23, 202639m 3s
  More actions for workflow run 3327

• Complex mask load store

  completed successfully:
  RISC-V RVV cross-compilation build#3326:Pull request#1429synchronizebyemrys53
  emrys53:complex_mask_load_store

  Oct 16, 202622m 10s
  More actions for workflow run 3326

• Fix SSE2 build on MSVC by renaming a variable. (#1428)

  completed successfully:
  RISC-V RVV cross-compilation build#3325:Commit457dcf7pushedbyJohanMabille
  master

  Oct 16, 202618m 2s
  More actions for workflow run 3325

• Allow setting XSIMD_WITH_SSE3, SSSE3, SSE4_1 and SSE4_2 manually with…

  cancelled:
  RISC-V RVV cross-compilation build#3324:Commitf92d002pushedbyJohanMabille
  master

  Oct 16, 20262m 29s
  More actions for workflow run 3324

• Allow setting XSIMD_WITH_SSE3, SSSE3, SSE4_1 and SSE4_2 manually with MSVC

  completed successfully:
  RISC-V RVV cross-compilation build#3323:Pull request#1430openedbykou
  kou:sse-msvc

  Oct 16, 202617m 1s
  More actions for workflow run 3323

• Complex mask load store

  failed:
  RISC-V RVV cross-compilation build#3322:Pull request#1429openedbyemrys53
  emrys53:complex_mask_load_store

  Oct 15, 202619m 52s
  More actions for workflow run 3322

• Fix SSE2 build on MSVC by renaming a variable.

  completed successfully:
  RISC-V RVV cross-compilation build#3321:Pull request#1428synchronizebydegasus
  degasus:avoid_ms_macros

  Oct 15, 202622m 52s
  More actions for workflow run 3321

• Fix SSE2 build on MSVC by renaming a variable.

  completed successfully:
  RISC-V RVV cross-compilation build#3320:Pull request#1428openedbydegasus
  degasus:avoid_ms_macros

  Oct 15, 202613m 40s
  More actions for workflow run 3320

• Fix 8-bit fixed right shifts and rotations of signed integers

  completed successfully:
  RISC-V RVV cross-compilation build#3319:Commit514204fpushedbyDiamonDinoia
  master

  Oct 14, 202624m 40s
  More actions for workflow run 3319

• Fix 8-bit fixed right shifts and rotations of signed integers

  completed successfully:
  RISC-V RVV cross-compilation build#3318:Pull request#1421synchronizebyArthur031221
  Arthur031221:fix-8bit-rshift-signed-rotations

  Oct 14, 202623m 35s
  More actions for workflow run 3318

• feat: add per-lane popcount on batch

  completed successfully:
  RISC-V RVV cross-compilation build#3317:Pull request#1401synchronizebyDiamonDinoia
  DiamonDinoia:feat/popcount

  Oct 13, 202618m 21s
  More actions for workflow run 3317

• added the missing namespace detail for some avx2 functions

  completed successfully:
  RISC-V RVV cross-compilation build#3316:Commitc01a751pushedbyserge-sans-paille
  master

  Oct 13, 202618m 51s
  More actions for workflow run 3316

• added the missing namespace detail for some avx2 functions

  completed successfully:
  RISC-V RVV cross-compilation build#3315:Pull request#1426openedbyemrys53
  emrys53:bug/missing_detail_namespace

  Oct 13, 202621m 55s
  More actions for workflow run 3315

• Fix nearbyint and rint in directed rounding modes

  requires action with the application:
  RISC-V RVV cross-compilation build#3314:Pull request#1425openedbymonishpeddapally
  monishpeddapally:fix/current-rounding-mode

  Oct 12, 2026Action required
  More actions for workflow run 3314

• Fix 8-bit fixed right shifts and rotations of signed integers

  completed successfully:
  RISC-V RVV cross-compilation build#3313:Pull request#1421synchronizebyArthur031221
  Arthur031221:fix-8bit-rshift-signed-rotations

  Oct 9, 202616m 26s
  More actions for workflow run 3313

• Fix 8-bit fixed right shifts and rotations of signed integers

  completed successfully:
  RISC-V RVV cross-compilation build#3312:Pull request#1421synchronizebyArthur031221
  Arthur031221:fix-8bit-rshift-signed-rotations

  Oct 9, 202636m 4s
  More actions for workflow run 3312

• feat: add per-lane popcount on batch

  completed successfully:
  RISC-V RVV cross-compilation build#3311:Pull request#1401synchronizebyDiamonDinoia
  DiamonDinoia:feat/popcount

  Oct 9, 202617m 39s
  More actions for workflow run 3311

• Fix 8-bit fixed right shifts and rotations of signed integers

  requires action with the application:
  RISC-V RVV cross-compilation build#3310:Pull request#1421synchronizebyArthur031221
  Arthur031221:fix-8bit-rshift-signed-rotations

  Oct 8, 2026Action required
  More actions for workflow run 3310

• fixed signed zero issue in neg function for vxe

  completed successfully:
  RISC-V RVV cross-compilation build#3309:Commitb8df57bpushedbyserge-sans-paille
  master

  Oct 8, 202618m 29s
  More actions for workflow run 3309

• Fix/neg avx512f

  completed successfully:
  RISC-V RVV cross-compilation build#3308:Pull request#1423synchronizebyemrys53
  emrys53:fix/neg-avx512f

  Oct 8, 202616m 52s
  More actions for workflow run 3308

• Fix/neg avx512f

  completed successfully:
  RISC-V RVV cross-compilation build#3307:Pull request#1423openedbyemrys53
  emrys53:fix/neg-avx512f

  Oct 7, 202635m 45s
  More actions for workflow run 3307

• Fix 8-bit fixed right shifts and rotations of signed integers

  requires action with the application:
  RISC-V RVV cross-compilation build#3306:Pull request#1421synchronizebyArthur031221
  Arthur031221:fix-8bit-rshift-signed-rotations

  Oct 7, 2026-1s
  More actions for workflow run 3306

• Fix 8-bit fixed right shifts and rotations of signed integers

  requires action with the application:
  RISC-V RVV cross-compilation build#3305:Pull request#1421synchronizebyArthur031221
  Arthur031221:fix-8bit-rshift-signed-rotations

  Oct 5, 2026Action required
  More actions for workflow run 3305

• Fix 8-bit fixed right shifts and rotations of signed integers

  requires action with the application:
  RISC-V RVV cross-compilation build#3304:Pull request#1421synchronizebyArthur031221
  Arthur031221:fix-8bit-rshift-signed-rotations

  Oct 3, 2026Action required
  More actions for workflow run 3304