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…y its CTR counter past the engine's 32-bit wrap
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Fenrir Automated Review — PR #12055
Scan targets checked: wolfcrypt-src, wolfcrypt-bugs, wolfcrypt-port-bugs, wolfssl-src, wolfssl-bugs
Not reviewed (no scan target covers them): .github/workflows/mpfs-athena-compile.yml, configure.ac, wolfcrypt/src/port/microchip/README.md
Coverage: 4 of 4 in-scope changed file(s) opened by the reviewer
Fenrir result: Approved ✅
No new issues found in the changed files.
Advisory only — this automated result does not count as a GitHub approval.
Review tier: Max
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Description
AES-XTS is AES-ECB over tweak-masked data, and
_AesXtsHelper()already issues one bulk ECB call per XTS call through the crypto callback, so the Athena F5200 port needs an ECB case and no XTS code. Validating it on the MPFS250TS Video Kit also turned up two bugs that this fixes.mpfs_athena.c:WC_CIPHER_AES_ECBfor AES-256, both directions.WC_MPFS_ATHENA_AES_MIN_SZ(32) declines shorter requests to software: XTS sends its tweak and ciphertext-stealing tail as one-blockwc_AesEncryptDirect()requests, and one engine round trip per block loses to software. The self-test covers distinct and in-place buffers, the shape XTS uses.wc_AesCtrEncrypt(). Each transfer now stops at the wrap andaes->regis advanced in software; the self-test runs a stream across it.aes.c: the 64-bitGMULT()table path reads at odd offsets and had noWOLFSSL_USE_ALIGNguard, unlike the 32-bit path; a strict-alignment 64-bit target now takes the byte loop, and the unreachable copy of it is removed.configure.acturns on AES-ECB with--with-mpfs-athena --enable-aesxts; CI legs for ECB alone and the XTS build; README.AES-128 and AES-192 requests stay in software, as before.
Testing
MPFS250TS Video Kit, E51 bare metal under wolfBoot's test-app: the self-test, the full
wolfcrypt_test()(AES-XTS through the engine, the AES-CTR wrap vector that failed before, AES-GCM where it trapped before) and the benchmark. Host:make checkwith--enable-aesxts --enable-aesecb --enable-cryptocb,testwolfcryptwith and withoutWOLFSSL_USE_ALIGN, every port CI leg compiled.