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🟡 Changes recommended
The TSIP conversion lacks committed regression tests through both verification entry points covering truncated DER, sign-padding zeros, and 31/32/33-byte components, with assertions for exact raw output and rejection before driver invocation.
1 open issue
What changed in this PR
This PR hardens input validation in wolfSSL’s Renesas TSIP port, addressing unsafe signature conversion, curve mismatches, and invalid TLS 1.3 Finished lengths.
Changes:
- Replaces fixed-offset ECDSA signature conversion with a shared DER parser that validates component sizes and right-aligns the output.
- Checks ECC key metadata, curve compatibility, and size before hardware verification, allowing software fallback when unsupported.
- Rejects Finished messages that are not 32 bytes before passing them to TSIP.
| File | Description |
|---|---|
| wolfcrypt/src/port/Renesas/renesas_tsip_util.c | Adds shared signature parsing, ECC curve validation, and Finished-length checks. |
Review effort: Balanced
| return BAD_FUNC_ARG; | ||
| } | ||
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| ret = wc_ecc_sig_to_rs(sig, sigSz, r, &rLen, s, &sLen); |
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ChangeLog entries are maintained separately and are not included in this PR.
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