x86_64 asm: load 32-bit parameters as 32-bit and ArrowLake/LunarLake change

.wolfssl_known_macro_extras

@@ -841,6 +841,7 @@ WC_ASYNC_THREAD_BIND
 WC_BENCH_AES_IV_SWEEP
 WC_BLINDING_NO_RNG_ACKNOWLEDGE_WEAKNESS
 WC_CACHE_RESISTANT_BASE64_TABLE
+WC_CPUID_NO_TUNING
 WC_DISABLE_RADIX_ZERO_PAD
 WC_DRBG_BANKREF
 WC_FIPS_ED25519CTX_NOT_APPROVED
@@ -1482,6 +1483,7 @@ __ghc__
 __ghs__
 __has_attribute
 __has_include
+__has_warning
 __hpux__
 __i386
 __i386__

tests/unit-mcdc/test_chacha_whitebox.c

@@ -57,20 +57,21 @@
  * The AVX-512 ChaCha work replaced that flat if/else with a length-and-feature
  * ladder in wc_Chacha_Process, five compound decisions deep:
  *
- *   msglen <= CHACHA_CHUNK_BYTES && IS_INTEL_AVX512_VL(f) == 0 &&
+ *   msglen <= CHACHA_CHUNK_BYTES && !CHACHA_USE_AVX512_VL(f) &&
  *       IS_INTEL_AVX1(f)                                   -> 1-block AVX1
- *   IS_INTEL_AVX512_VL(f) == 0 && msglen < 4*CHUNK &&
+ *   !CHACHA_USE_AVX512_VL(f) && msglen < 4*CHUNK &&
  *       IS_INTEL_SSSE3(f)                                  -> SSSE3
- *   IS_INTEL_AVX512_VL(f) == 0 && msglen < 4*CHUNK         -> scalar x64
+ *   !CHACHA_USE_AVX512_VL(f) && msglen < 4*CHUNK           -> scalar x64
  *   chacha_avx512_beneficial(f) && msglen >= 16*CHUNK      -> 512-bit zmm
- *   IS_INTEL_AVX512_VL(f) && msglen < 8*CHUNK              -> AVX-512VL
+ *   CHACHA_USE_AVX512_VL(f) && msglen < 8*CHUNK            -> AVX-512VL
  *
  * plus the predicate chacha_avx512_beneficial(): IS_INTEL_AVX512(f) &&
- * IS_INTEL_VAES(f).
+ * IS_INTEL_VAES(f). CHACHA_USE_AVX512_VL(f) is IS_INTEL_AVX512_VL(f) when the
+ * AVX-512VL kernel is built (HAVE_INTEL_AVX512) and 0 otherwise.
  *
  * Two inputs decide all of them: the message length and the cpuid mask. One
  * host only ever supplies one mask -- on an AVX-512VL machine every
- * "IS_INTEL_AVX512_VL(f) == 0" operand is permanently false, which pins three
+ * "!CHACHA_USE_AVX512_VL(f)" operand is permanently false, which pins three
  * of the five decisions to a single outcome no matter what lengths the tests
  * use, and on a machine without AVX-512 the last two are pinned the other way.
  * wb_chacha_process_case() drives one (mask, length) pair; the table in

tests/unit-mcdc/test_sha3_whitebox.c

@@ -108,13 +108,17 @@ static void wb_sha3_dispatch(void)
     wb_init_with(CPUID_BMI1,              NULL);   /* [T,F] */
     wb_init_with(0,                       NULL);   /* [F,-] -> C block */
 
-    /* SHA3_USE_AVX2(f) = IS_INTEL_AVX2(f) && IS_CPU_INTEL(f).
+    /* SHA3_USE_AVX2(f) = IS_INTEL_AVX2(f) && IS_CPU_INTEL(f) &&
+     *                    !IS_CPU_SLOW_AVX2_SHA3(f).
      *   The [T,T] row cannot come from real cpuid on a non-Intel host, so
      *   neither operand's pair completes without forcing the vendor bit:
      *   AVX2-capable AMD reports [T,F], the same row as the AVX2-only call
      *   above. Supply [T,T]; it pairs with CPUID_AVX2 ([T,F]) for operand 1
      *   and with the BMI rows ([F,-]) for operand 0. */
     wb_init_with(CPUID_AVX2 | CPUID_INTEL, NULL);
+    /* Third operand, !IS_CPU_SLOW_AVX2_SHA3(f): [T,T,T] pairs with the row
+     *   above for its independence (Arrow Lake: AVX2 Keccak skipped). */
+    wb_init_with(CPUID_AVX2 | CPUID_INTEL | CPUID_SLOW_AVX2_SHA3, NULL);
 
     /* 874: (sha3_block_n != NULL) && (blocks > 0), in Sha3Update. MC/DC needs
      *   cond0's independence pair -- both the NULL and non-NULL multi-block

tests/unit-mcdc/test_wc_mldsa_whitebox.c

@@ -1080,9 +1080,12 @@ static void wb_dispatch_rows(void)
     /* USE_INTEL_AVX512(f) is itself IS_INTEL_AVX512(f) && IS_INTEL_AVX512_BW(f)
      * (cpuid.h), so each AVX512 dispatch is a three-condition decision and the
      * F and BW bits need to be cleared separately.  SHA3_USE_AVX2(f) is
-     * IS_INTEL_AVX2(f) && IS_CPU_INTEL(f): its vendor operand is false on any
-     * AMD host, so CPUID_INTEL is forced on for the rows that need its true
-     * side -- the arm behind it is plain AVX2, which runs anywhere AVX2 does. */
+     * IS_INTEL_AVX2(f) && IS_CPU_INTEL(f) && !IS_CPU_SLOW_AVX2_SHA3(f): its
+     * vendor operand is false on any AMD host, so CPUID_INTEL is forced on for
+     * the rows that need its true side -- the arm behind it is plain AVX2,
+     * which runs anywhere AVX2 does.  The host's tuning bits are cleared on
+     * every row so the rows mean the same on Arrow Lake, and one row sets
+     * CPUID_SLOW_AVX2_SHA3 for that operand's true side. */
     static const struct {
         cpuid_flags_t set;
         cpuid_flags_t clear;
@@ -1110,6 +1113,9 @@ static void wb_dispatch_rows(void)
                        CPUID_AVX512_VBMI | CPUID_BMI2 |
                        CPUID_AVX2,                 0 },  /* portable C       */
         { 0,           CPUID_INTEL,                0 },  /* non-Intel vendor */
+        { CPUID_INTEL | CPUID_SLOW_AVX2_SHA3,
+                       CPUID_AVX512 | CPUID_AVX512_BW |
+                       CPUID_AVX512_VBMI,          0 },  /* AVX2, slow Keccak */
     };
 
     if (wc_InitRng(&rng) != 0) {
@@ -1120,6 +1126,7 @@ static void wb_dispatch_rows(void)
     for (i = 0; i < sizeof(rows) / sizeof(rows[0]); i++) {
         cpuid_flags = WC_CPUID_INITIALIZER;
         (void)cpuid_get_flags_ex(&cpuid_flags);
+        cpuid_flags &= (cpuid_flags_t)~(CPUID_SLOW_VAES | CPUID_SLOW_AVX2_SHA3);
         cpuid_flags |= rows[i].set;
         cpuid_flags &= (cpuid_flags_t)~rows[i].clear;
         wb_intr_ret = rows[i].intr;

wolfcrypt/benchmark/benchmark.c

@@ -5168,6 +5168,8 @@ static void print_cpu_features(void)
     if (IS_INTEL_SHA(cpuid_flags))    printf(" sha");
     if (IS_INTEL_VAES(cpuid_flags))   printf(" vaes");
     if (IS_INTEL_AVX512(cpuid_flags)) printf(" avx512");
+    if (IS_CPU_SLOW_VAES(cpuid_flags)) printf(" (slow-vaes)");
+    if (IS_CPU_SLOW_AVX2_SHA3(cpuid_flags)) printf(" (slow-avx2-sha3)");
 #endif
 #ifdef __aarch64__
     printf("Aarch64 -");