H5 and RT700 conformance NSPE buffer lies outside guest0, so i052/i053 skip the range-end check #80

Summary

The STM32H563 and MIMXRT700 conformance configs place the NSPE MMIO buffer outside guest0's RAM window, so Arm FF-M IPC tests i052 and i053 can pass without checking the range-end validation they target.

• port/stm32h563/conformance/pal_config.h: NSPE_MMIO_0_START 0x20038F00, guest0 RAM 0x20000000-0x2000FFFF
• port/mimxrt700/conformance/pal_config.h: NSPE_MMIO_0_START 0x20198F00, guest0 RAM 0x20100000-0x2013FFFF

i052/i053 pass PLATFORM_NSPE_MMIO_START as a valid buffer base with a size that runs past the driver partition MMIO, expecting the SPM to reject the bad end. With an invalid base, the SPM rejects on the start, so the test passes while the end check goes untested.

MCXN947 had the same issue and was fixed in #79 (commit a097417): the buffer moved into guest0's window, and an #error guard in port/mcxn947/conformance/conf_nvm_sync.c keeps it there. That port's confboot still reports 85 passed, 4 skipped, 0 failed.

Commit or release

upstream/main at 034c89e (H5 and RT700 configs unchanged by #79)

Target

STM32H563 and MIMXRT700 (M33MU and silicon)

Crypto engine

Both (hsm and native)

Steps to reproduce

1. Compare NSPE_MMIO_0_START/_END in each port's conformance/pal_config.h with WT_GUEST0_RAM_BASE and WT_GUEST_RAM_SIZE in its memory_map.h.
2. tests/target/run_suite.sh m33mu confboot and tests/target/run_suite.sh rt700-m33mu confboot

Expected and actual behavior

Expected: the NSPE buffer lies inside guest0's RAM window, so only the end of the i052/i053 range is invalid.

Actual: the base is outside guest0's window, so the tests pass on the start check alone.

Acceptance: move both buffers into guest0's window, add the same #error guard as MCXN947, and get confboot at 85/4/0 on both ports with both engines.

Logs

N/A (found by config review; Copilot comment on #79)