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W2: Own interrupt lines and peripherals per partition on the AArch64 SPMC #67
Description
Context
Plan item W2 of the AArch64 level 3 plan (tracking #46). The Armv8-M ports own each partition's interrupt lines and refuse partition access to SPM peripherals; the AArch64 SPMC needs the same before its manifests can declare isolation level 3.
Origin
#29 rebase onto main's level 3 work; the AArch64 level 3 plan
What is needed
wt_arch_secure_irq_claimon the AArch64 SPMC routes through the sharedwt_irq_claim: disable, Secure Group 0, clear pending, read back, fail closed (GICv2 and GICv3)wt_platform_sp_peripheralsfor qemuvirt and versal: no partition owns MMIO today, so the table refuses every DEVICE resource- QEMU twins of the M33MU
periphspneg(a partition reads the Secure UART and faults) andperiphneg(the Normal world probes Secure MMIO; SKIP on versal-virt, which has no XPPU model, see Add a Versal hardware port with an XMPU and XPPU Normal-world fence #45)
Blockers and dependencies
None. The interrupt claim is done on wolfTrust-dev2; the twins follow it.
Acceptance criteria
periphspnegpasses on virt gicv2 a35, virt gicv3 a72 and versal-virt with both engines;periphnegpasses on virt and SKIPs on versal-virtffa-sintand the ACSinterruptsgroup stay green- Skoll review and review-security clean on the change
Activity
aidangarske commentedon Oct 2, 2026
W2 progress, on wolfTrust-dev2 (#29):
Remaining: the refuse-all partition peripheral table and the
periphnegandperiphspnegtwins. They are in review now and land in the next push to #29.aidangarske commentedon Oct 3, 2026
Landed on wolfTrust-dev2 (#29):
periphspnegandperiphnegQEMU twins. A partition read of the SPM's secure UART takes a data abort at S-EL0 and fails closed. A Normal-world read of it is refused onvirtand skipped onxlnx-versal-virt, which models no XPPU (Add a Versal hardware port with an XMPU and XPPU Normal-world fence #45).wt_platform_sp_peripheralsstays an empty refuse-all table: no AArch64 partition owns MMIO. The ACS watchdog (INTID 56) is the SPM's virtual timer watchdog, and the secure UART belongs to the SPM.Remaining: nothing for W2 beyond the versal XPPU fence, which is tracked in #45.