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[spimem, flash, cadence_ospi, versal2, test] Add a SPI memory type with Cadence OSPI and NOR flash drivers - #64
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The whal_Reg_* helpers read and wrote through size_t, which is 64 bits on AArch64, so a write also changed the next register. They now always access one 32-bit register, as the header already said. Value and mask bits above bit 31 are dropped; reg.h and the driver guide say so. Adds core reg tests that check each helper touches only its own register and drops bits above bit 31, that an update clears field bits, and that a poll ignores bits outside the mask, retries until the field matches, waits for bits to clear, and times out. Builds src/reg.c in the core tests.
…opt-in whal_Reg32_* and whal_Reg64_* take a uintptr_t base, a uint32_t offset and values of the register's width, so the access width is explicit and no value is cast. whal_Reg64_* exists only where a 64-bit access is one access (WHAL_HAVE_REG64). The size_t whal_Reg_* API is now only built with WHAL_CFG_REG_LEGACY. It does 32-bit accesses through whal_Reg32_*. Where size_t is 64 bits, a value or mask above bit 31 returns WHAL_EINVAL and nothing is written; Write, Update and Get now return whal_Error. Where size_t is 32 bits there is no check, and the code is the same as before. The boards in boards/ define WHAL_CFG_REG_LEGACY, so the existing drivers build unchanged. Core tests cover Reg32, Reg64 and the legacy API, including the range checks, and check that whal_Reg_* is not defined without WHAL_CFG_REG_LEGACY. The driver and test guides use whal_Reg32_*.
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Per review, keep only whal_Reg32_* and whal_Reg64_*. All drivers, board files and tests now call whal_Reg32_*. Device base fields and base locals are uintptr_t. Variables read with whal_Reg32_Get are uint32_t.
…th Cadence OSPI and NOR flash drivers Add whal_SpiMem, a device type for flash controllers that send one complete command per call (opcode, address, dummy cycles, data) and drive chip select themselves, so they cannot act as a byte-stream SPI bus. Each operation carries its bus mode, as in Linux spi-mem: the lines for the opcode, address and data, and DTR. MaxDataSz reports how much data one command can carry. Adds the dispatch layer and a "SPI Memory" section in the driver guide. Add a spimem driver for the Cadence OSPI controller (AMD Versal Gen 2 OSPI): each operation runs as a STIG command with up to 8 data bytes, waiting for the done bit and then CONFIG idle; reads with an address are split into 8-byte commands. Init sets the clock, chip select and read capture from the configuration and turns off DTR, the PHY and dual-byte opcodes an earlier boot stage may have left on. Exec sets each operation's lines in the instruction registers and DTR in CONFIG. An optional DMA hook reads the aligned middle of a read with an indirect read; the Versal Gen 2 OSPI DMA provides it (whal_Versal2_OspiDma_Arm/Wait). Adds the Versal Gen 2 platform header (OSPI part). Add whal_SpiMemNor_Flash, a whal_Flash driver on a whal_SpiMem controller with configurable opcodes, address size, page and erase sizes: writes are split at page edges and at the controller's largest program, each piece waits for the write enable latch and then for the flash to finish, and with WHAL_SPIMEM_NOR_FLAG_FSR the Micron flag status register is checked and cleared on errors. Init checks the JEDEC ID (optionally against an expected ID) and, with WHAL_SPIMEM_NOR_FLAG_RESET, resets a flash that does not answer in 1-bit mode: 66h/99h, also as octal DTR operations for a flash left in octal DDR, and optionally the Micron volatile configuration set to 1-bit with the address size the flag status register reports. whal_SpiMemNor_Flash_ReadId reads the ID. Core host tests cover the dispatch layer, the Cadence driver against an emulated register block, the NOR driver against a fake flash that is busy after each program or erase, and the DMA hook.
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Adds
spimem, a device type for flash controllers that send one whole command at a time (opcode, address, dummy cycles, data) and drive chip select themselves, so they can't be a byte-streamwhal_Spibus. Each operation carries its bus mode (lines per phase and DTR), as in Linux spi-mem. Also adds a Cadence OSPI driver for it, the AMD Versal Gen 2 OSPI DMA read hook, and a NOR flash driver that works on anyspimemcontroller. Depends on #62 ([reg, test]); until that merges, review only the last commit.Changes
spimem/spimem.h,src/spimem/spimem.c: the type (Init,Deinit,Exec,MaxDataSz),whal_SpiMemOpwithopLines/addrLines/dataLines/dtr,WHAL_SPIMEM_OP_INIT_1BIT, dispatch, and a "SPI Memory" section indocs/writing_a_driver.md.spimem/cadence_ospi_spimem: each op is one STIG command (up to 8 data bytes, done bit then CONFIG idle); reads with an address are split; bus mode set per op in DEV_INSTR_RD/WR and CONFIG DTR; Init sets clock, chip select and read capture and turns off DTR/PHY left by a boot stage; optional DMA hook for the aligned middle of reads (AM026 ch. 66, AM028 OSPI).spimem/versal2_ospi_dma: the Versal Gen 2 OSPI DMA as that hook, with cache callbacks.flash/spimem_nor_flash:whal_Flashonspimemwith configurable opcodes and sizes, page-split writes, Micron flag status errors, an optional expected ID, and optional recovery at Init (66h/99hreset, also in octal DDR, then Micron volatile 1-bit); never writes nonvolatile config.platform/amd/versal2.h: OSPI base and indirect-read values.Tests
New core tests for the dispatch, the Cadence driver (emulated registers), the NOR driver (fake flash, incl. recovery cases) and the DMA hook.
tests/core: 186 / 168 (+4 skipped, need the emulator tick) / 186 pass in the three CI builds. All drivers build for AArch64 with-Wall -Wextra -Werror, and run on a VEK385 Rev B under wolfBoot (OSPI boot, A/B updates).