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[uart, pl011, versal2, test] Add an Arm PL011 UART driver - #63
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The whal_Reg_* helpers read and wrote through size_t, which is 64 bits on AArch64, so a write also changed the next register. They now always access one 32-bit register, as the header already said. Value and mask bits above bit 31 are dropped; reg.h and the driver guide say so. Adds core reg tests that check each helper touches only its own register and drops bits above bit 31, that an update clears field bits, and that a poll ignores bits outside the mask, retries until the field matches, waits for bits to clear, and times out. Builds src/reg.c in the core tests.
…opt-in whal_Reg32_* and whal_Reg64_* take a uintptr_t base, a uint32_t offset and values of the register's width, so the access width is explicit and no value is cast. whal_Reg64_* exists only where a 64-bit access is one access (WHAL_HAVE_REG64). The size_t whal_Reg_* API is now only built with WHAL_CFG_REG_LEGACY. It does 32-bit accesses through whal_Reg32_*. Where size_t is 64 bits, a value or mask above bit 31 returns WHAL_EINVAL and nothing is written; Write, Update and Get now return whal_Error. Where size_t is 32 bits there is no check, and the code is the same as before. The boards in boards/ define WHAL_CFG_REG_LEGACY, so the existing drivers build unchanged. Core tests cover Reg32, Reg64 and the legacy API, including the range checks, and check that whal_Reg_* is not defined without WHAL_CFG_REG_LEGACY. The driver and test guides use whal_Reg32_*.
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Per review, keep only whal_Reg32_* and whal_Reg64_*. All drivers, board files and tests now call whal_Reg32_*. Device base fields and base locals are uintptr_t. Variables read with whal_Reg32_Get are uint32_t.
Add a polled Arm PL011 UART driver (pl011_uart) with single-instance and direct API mapping support, baud divisor helper macros, and a platform header for AMD Versal Gen 2 with the UART0 and UART1 bases. Init always sets the baud and format from the configuration. Init and Deinit turn the UART off and wait for the last byte to go out before changing the setup. A new core host test runs the driver against an emulated register block and checks the divisor math, Init (also over a setup an earlier boot stage left), Deinit, Send, Recv errors, argument checks, timeouts, and that each access touches only its own 32-bit register.
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Adds a polled driver for the Arm PL011 UART (
uart/pl011_uart), the UART used on AMD Versal Gen 2 (AM026 ch. 63; register map in AM028, UART module). It follows the existing UART drivers: the board computes the divisor register values with header macros, asbrris computed for the STM32 drivers, and Init always programs them.Also adds the AMD Versal Gen 2 platform header with the UART0 and UART1 bases.
Depends on the
[reg, test]32-bit register access PR. (#62)Changes
wolfHAL/uart/pl011_uart.h,src/uart/pl011_uart.c:whal_Pl011_Uart_Cfg { ibrd, fbrd, lcrH, timeout }.WHAL_PL011_UART_IBRD(clk, baud)/WHAL_PL011_UART_FBRD(clk, baud):the divisor is clk / (16 x baud) with a 6-bit fraction (AM026 ch. 63
p670), from one rounded value round(clk x 4 / baud), so the fraction
carries into the integer part when it rounds up to 64.
WHAL_PL011_UART_LCRH_*bits andWHAL_PL011_UART_LCRH_8N1_FIFO(AM028 UART LINE_CTRL).
bits, AM026 ch. 63 p670), turns the UART off and waits for BUSY to clear
before changing the setup (AM026 ch. 63 p669), writes IBRD and FBRD,
then LCR_H (the divisors take effect on the LCR_H write, Arm PL011 TRM,
UARTLCR_H), then turns the UART, TX and RX on.
empty and BUSY to clear (AM026 ch. 63 p668).
WHAL_EHARDWAREon a framing, parity,break or overrun error and clears it.
WHAL_ENOTSUP.WHAL_CFG_PL011_UART_SINGLE_INSTANCEandWHAL_CFG_PL011_UART_DIRECT_API_MAPPING, as in the other drivers.wolfHAL/platform/amd/versal2.h(new):WHAL_VERSAL2_UART0_BASE(
0xF1920000),WHAL_VERSAL2_UART1_BASE(0xF1930000),WHAL_VERSAL2_UART_DRIVER.tests/core/test_pl011_uart.c(new), withtests/core/main.c,tests/core/Makefileandtests/README.md. The driver runs against anemulated register block:
stage left on with another setup (Init sets it up again), bad divisors,
BUSY timeout.
ENOTSUP, TX FIFO and drain timeouts, Recv timeout.