[pull] master from golang:master

src/cmd/compile/internal/amd64/ssa.go

@@ -2165,7 +2165,7 @@ func simdVgpvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
 }
 func simdVgpvImm(s *ssagen.State, v *ssa.Value) *obj.Prog {
 	// within simdgen, the choice of intrinsic shape and the output
-	// intruction format are linked.  In the case of VgpImm, there is
+	// instruction format are linked.  In the case of VgpImm, there is
 	// a difference in the intrinsic, but no difference in the
 	// instruction, it is just like VgpvImm8.
 	//
@@ -2276,7 +2276,7 @@ func simdVgpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
 
 func simdVgpImm(s *ssagen.State, v *ssa.Value) *obj.Prog {
 	// within simdgen, the choice of intrinsic shape and the output
-	// intruction format are linked.  In the case of VgpImm, there is
+	// instruction format are linked.  In the case of VgpImm, there is
 	// a difference in the intrinsic, but no difference in the
 	// instruction, it is just like VgpImm8.
 	return simdVgpImm8(s, v)

src/cmd/compile/internal/arm64/ssa.go

@@ -2163,6 +2163,12 @@ func simdZ2kvPred(s *ssagen.State, v *ssa.Value, arng int16) *obj.Prog {
 	switch d {
 	case x:
 	case y:
+		// Only reachable for a commutative operation: a non-commutative one is
+		// marked resultInArg0, which pins the destination to arg0. Swapping the
+		// sources of one would compute y-x where x-y was asked for.
+		if v.Op.ResultInArg0() {
+			v.Fatalf("destination is arg1 of resultInArg0 op %v", v.Op)
+		}
 		x, y = y, x
 	default:
 		mp := s.Prog(arm64.AZMOVPRFX)
@@ -2181,6 +2187,35 @@ func simdZ2kvPred(s *ssagen.State, v *ssa.Value, arng int16) *obj.Prog {
 	return p
 }
 
+// simdZkv emits a predicated-only SVE unary operation standing in for an
+// unpredicated one, e.g. ZABS Z0.B, P0.M, Z1.B. SSA provides arg0=x and
+// arg1=the governing predicate, which the lowering rule synthesized as
+// all-true. With every lane active, merging predication leaves nothing of the
+// destination behind, so the operation is unpredicated in effect.
+func simdZkv(s *ssagen.State, v *ssa.Value, arng int16) *obj.Prog {
+	return sveUnaryPred(s, v, arng, v.Args[0].Reg(), v.Args[1].Reg(), arm64.PRED_M)
+}
+
+// simdZ2kvPredResultInArg0 emits the merging form of a predicated SVE unary
+// operation, e.g. ZABS Z1.B, P0.M, Z0.B. SSA provides arg0=the value the
+// inactive lanes keep, arg1=x, arg2=mask, and resultInArg0 puts that value in
+// the destination. The instruction is constructive -- it names its destination
+// apart from its source -- so merging into that destination needs no MOVPRFX.
+func simdZ2kvPredResultInArg0(s *ssagen.State, v *ssa.Value, arng int16) *obj.Prog {
+	return sveUnaryPred(s, v, arng, v.Args[1].Reg(), v.Args[2].Reg(), arm64.PRED_M)
+}
+
+// sveUnaryPred emits a predicated SVE unary operation: OP Zn.T, Pg/<qual>, Zd.T.
+func sveUnaryPred(s *ssagen.State, v *ssa.Value, arng int16, zn, pg int16, qual int16) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = zregArng(zn, arng)        // Zn
+	p.AddRestSourceReg(pregMask(pg, qual)) // Pg/M or Pg/Z
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = zregArng(v.Reg(), arng) // Zd
+	return p
+}
+
 // simdZ3kvPredResultInArg0 emits an SVE merging-predicated binary operation
 // whose inactive lanes come from a value that is neither of its sources, e.g.
 // x.Add(y).IfElse(mask, z). SSA provides arg0=z, arg1=x, arg2=y, arg3=mask, and

src/cmd/compile/internal/ir/expr.go

@@ -1212,28 +1212,15 @@ func promotedWrapperSym(wrapper, wrappee *types.Type, msym *types.Sym, offset in
 		recvMode = "n"
 	}
 
-	rsym := wrapper.Sym()
-	if wrapper.IsPtr() {
-		if rsym != nil {
-			base.Fatalf("declared pointer receiver type: %v", wrapper)
-		}
-		rsym = wrapper.Elem().Sym()
-	}
-	rpkg := Pkgs.Go
-	if rsym != nil {
-		rpkg = rsym.Pkg
-	}
+	wrappeeMethod := ReceiverMethodSym(wrappee, msym)
 
 	var b bytes.Buffer
-	fmt.Fprintf(&b, ".embed.%-S.", wrappee)
-	if !types.IsExported(msym.Name) {
-		b.WriteString(msym.Pkg.Prefix)
-		b.WriteString(".")
-	}
-	b.WriteString(msym.Name)
-	fmt.Fprintf(&b, ".%d%s.%d", derefs, recvMode, offset)
+	fmt.Fprintf(&b, ".embed.%d%s.%d.", derefs, recvMode, offset)
+	b.WriteString(wrappeeMethod.Pkg.Prefix)
+	b.WriteString(".")
+	b.WriteString(wrappeeMethod.Name)
 
-	sym := rpkg.LookupBytes(b.Bytes())
+	sym := wrappeeMethod.Pkg.LookupBytes(b.Bytes())
 	sym.SetFunc(true)
 	return sym
 }

src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

@@ -203,6 +203,7 @@ func init() {
 		fp31           = regInfo{inputs: []regMask{fp, fp, fp}, outputs: []regMask{fp}}
 		fp2flags       = regInfo{inputs: []regMask{fp, fp}}
 		fp1flags       = regInfo{inputs: []regMask{fp}}
+		fp1predfp      = regInfo{inputs: []regMask{fp, pred}, outputs: []regMask{fp}}
 		fp2predpred    = regInfo{inputs: []regMask{fp, fp, pred}, outputs: []regMask{pred}}
 		fp2predfp      = regInfo{inputs: []regMask{fp, fp, pred}, outputs: []regMask{fp}}
 		fp3predfp      = regInfo{inputs: []regMask{fp, fp, fp, pred}, outputs: []regMask{fp}}
@@ -902,7 +903,7 @@ func init() {
 		pkg:                "cmd/internal/obj/arm64",
 		genfile:            "../../arm64/ssa.go",
 		genSIMDfile:        "../../arm64/simdssa.go ../../arm64/simdssa_sve.go",
-		ops:                append(append(ops, simdARM64Ops(fp11, fp21, fp31, fpgp, fpgpfp, fp21)...), simdARM64SVEOps(fp11, fp21, fp2predpred, fp2predfp, fp2predfp, fp3predfp)...),
+		ops:                append(append(ops, simdARM64Ops(fp11, fp21, fp31, fpgp, fpgpfp, fp21)...), simdARM64SVEOps(fp11, fp21, fp1predfp, fp2predpred, fp2predfp, fp2predfp, fp3predfp)...),
 		blocks:             blocks,
 		regnames:           regNamesARM64,
 		ParamIntRegNames:   "R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15",