DNS stub resolver, proxy and router with support for DoT, DoH, DoQ, and DTLS

Education kit for teaching computer architecture with a 5-stage Arm-based Verilog core and hands-on labs (educational)

The Refreshingly Simple Cross-Platform C++ Dataflow / Patching / Pipelining / Graph Processing / Stream Processing / Reactive Programming Framework

Multi-device OpenCL kernel load balancer and pipeliner API for C#. Uses shared-distributed memory model to keep GPUs updated fast while using same kernel on all devices(for simplicity).

Cross-Platform Graphical Tool for DSPatch

Asynchronous, HA (master-master) PostgreSQL driver on top of libpq.

MIT Course 6.004 - Computation Structures

Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

Efficiently pipeline, batch, and cache requests to any data source

DSPatch Component Repository

A two-stage predictive machine learning engine that forecasts the on-time performance of flights for 15 different airports in the USA based on data collected in 2016 and 2017.

FluidML is a lightweight framework for developing machine learning pipelines.

Kite: Architecture Simulator for RISC-V Instruction Set

A 5-stage pipelining RISC-V 32I simulator written in Rust.

An experiment in declaratively programming parallel pipelines of state machines.

Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.

Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals

Have pipeline in Erlang

A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.