Fix/divider correctness

[guosran]

Summary

Addresses #292 with a minimized divider operation fix. This PR updates DivRTL.py, its focused test, and lib/opt_type.py for the required REM opcodes.

Changes

• Handle DIV/REM zero divisors deterministically in simulation.
• Add REM and REM_CONST support.
• Add concrete examples as inline test comments.

No ExclusiveDiv backpressure rewrite, new ports, or new interfaces are included.

[tancheng]

Hi @guosran, "draft" means this is not yet ready for review, right?

[guosran]

Hi @guosran, "draft" means this is not yet ready for review, right?

Not yet, just a few more things to be done.

[guosran]

Concrete example:
For REM, PyMTL translates % into generated Verilog successfully:

  if ( divisor != 32'd0 ) begin
    div_remainder = dividend % divisor;
  end
  else
    div_remainder = 32'd0;

I restored the exact quotient path and use guarded % for the remainder path.

[tancheng]

Any idea why it failed translation?