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loader: Map all of RAM in the loader #511

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5168d72
loader(aarch64): pass PTs to enable MMU assembler
midnightveil May 6, 2026
e7453f5
(TOFIX: breaks SMP) loader(aarch64): dynamically allocate PTs
midnightveil May 18, 2026
717e633
loader(riscv64): apply the aarch64 treatment
midnightveil May 18, 2026
a600a29
[WIP] ram
midnightveil May 22, 2026
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21 changes: 8 additions & 13 deletions loader/src/aarch64/mmu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -12,18 +12,13 @@
#include "../cutil.h"
#include "../uart.h"

void el1_mmu_enable(void);
void el2_mmu_enable(void);
void el1_mmu_enable(uint64_t aarch64_pt_ttbr0_el1, uint64_t aarch64_pt_ttbr1_el1);
void el2_mmu_enable(uint64_t aarch64_pt_ttbr0_el2);

/* Paging structures for kernel mapping */
uint64_t boot_lvl0_upper[1 << 9] ALIGN(1 << 12);
uint64_t boot_lvl1_upper[1 << 9] ALIGN(1 << 12);
uint64_t boot_lvl2_upper[1 << 9] ALIGN(1 << 12);

/* Paging structures for identity mapping */
uint64_t boot_lvl0_lower[1 << 9] ALIGN(1 << 12);
uint64_t boot_lvl1_lower[1 << 9] ALIGN(1 << 12);
uint64_t boot_lvl2_lower[1 << 9] ALIGN(1 << 12);
/* Pointers to the top-level paging structures */
uint64_t aarch64_pt_ttbr0_el1;
uint64_t aarch64_pt_ttbr1_el1;
uint64_t aarch64_pt_ttbr0_el2;

int arch_mmu_enable(int logical_cpu)
{
Expand All @@ -37,9 +32,9 @@ int arch_mmu_enable(int logical_cpu)
LDR_PRINT("INFO", logical_cpu, "enabling MMU\n");
el = current_el();
if (el == EL1) {
el1_mmu_enable();
el1_mmu_enable(aarch64_pt_ttbr0_el1, aarch64_pt_ttbr1_el1);
} else if (el == EL2) {
el2_mmu_enable();
el2_mmu_enable(aarch64_pt_ttbr0_el2);
} else {
LDR_PRINT("ERROR", logical_cpu, "unknown EL for MMU enable\n");
}
Expand Down
28 changes: 17 additions & 11 deletions loader/src/aarch64/util64.S
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Original file line number Diff line number Diff line change
Expand Up @@ -302,14 +302,12 @@ BEGIN_FUNC(el1_mmu_disable)
*/
bl invalidate_icache

ldp x27, x28, [sp], #16
ldp x29, x30, [sp], #16
ret
END_FUNC(el1_mmu_disable)

BEGIN_FUNC(el2_mmu_disable)
stp x29, x30, [sp, #-16]!
stp x27, x28, [sp, #-16]!
mov x29, sp

/* Disable caches */
Expand All @@ -324,14 +322,18 @@ BEGIN_FUNC(el2_mmu_disable)
*/
bl invalidate_icache

ldp x27, x28, [sp], #16
ldp x29, x30, [sp], #16
ret
END_FUNC(el2_mmu_disable)

/*
* Enables the MMU for EL2.
* Takes two arguments the physical address for TTBR0_EL1 (x0) and TTBR1_EL1 (x1).
*/
BEGIN_FUNC(el1_mmu_enable)
stp x29, x30, [sp, #-16]!
stp x27, x28, [sp, #-16]!
/* move caller-saved to callee-saved registers */
mov x29, sp
mov x27, x0
mov x28, x1
Expand Down Expand Up @@ -359,10 +361,8 @@ BEGIN_FUNC(el1_mmu_enable)
msr tcr_el1, x10

/* Setup page tables */
adrp x8, boot_lvl0_lower
msr ttbr0_el1, x8
adrp x8, boot_lvl0_upper
msr ttbr1_el1, x8
msr ttbr0_el1, x27 /* argument 0 */
msr ttbr1_el1, x28 /* argument 1 */
isb

/* invalidate all TLB entries for EL1 */
Expand All @@ -372,14 +372,21 @@ BEGIN_FUNC(el1_mmu_enable)

enable_mmu sctlr_el1, x8

ldp x27, x28, [sp], #16
ldp x29, x30, [sp], #16
ret

END_FUNC(el1_mmu_enable)

/*
* Enables the MMU for EL2.
* Takes one argument, the physical address for TTBR0_EL2 (x0).
*/
BEGIN_FUNC(el2_mmu_enable)
stp x29, x30, [sp, #-16]!
stp x27, x28, [sp, #-16]!
/* move caller-saved to callee-saved registers */
mov x29, sp
mov x28, x0

/* Disable the MMU */
bl el2_mmu_disable
Expand All @@ -403,8 +410,7 @@ BEGIN_FUNC(el2_mmu_enable)
isb

/* Setup page tables */
adrp x8, boot_lvl0_lower
msr ttbr0_el2, x8
msr ttbr0_el2, x28 /* argument 0 */
isb

/* invalidate all TLB entries for EL2 */
Expand All @@ -423,9 +429,9 @@ BEGIN_FUNC(el2_mmu_enable)
dsb ish
isb

ldp x27, x28, [sp], #16
ldp x29, x30, [sp], #16
ret

END_FUNC(el2_mmu_enable)

.extern arm_secondary_cpu_c_entry
Expand Down
12 changes: 3 additions & 9 deletions loader/src/riscv/mmu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -8,15 +8,9 @@
#include <stdint.h>

#include "../arch.h"
#include "../cutil.h"

/* Paging structures for kernel mapping */
uint64_t boot_lvl1_pt[1 << 9] ALIGN(1 << 12);
uint64_t boot_lvl2_pt[1 << 9] ALIGN(1 << 12);
uint64_t boot_lvl3_pt[1 << 9] ALIGN(1 << 12);
/* Paging structures for identity mapping */
uint64_t boot_lvl2_pt_loader[1 << 9] ALIGN(1 << 12);

/* Pointers to the top-level paging structures */
uintptr_t riscv64_boot_lvl1_pt;

/*
* This is the encoding for the MODE field of the satp register when
Expand All @@ -36,7 +30,7 @@ int arch_mmu_enable(int logical_cpu)
asm volatile(
"csrw satp, %0\n"
:
: "r"(VM_MODE | (uintptr_t)boot_lvl1_pt >> RISCV_PGSHIFT)
: "r"(VM_MODE | riscv64_boot_lvl1_pt >> RISCV_PGSHIFT)
:
);
asm volatile("fence.i" ::: "memory");
Expand Down
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