Systematically define bit mask/offset/size for fields in CSRs#403
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June 15, 2026 17:54
Extend the read_only_csr_field! (and thereby read_write_csr_field!) macros to emit, for each bitfield, three associated constants on the CSR type: <FIELD>_SHIFT bit position (shift) of the field LSB <FIELD>_WIDTH number of bits in the field <FIELD>_MASK field-shifted bitmask Bit positions were previously only available as literals buried inside the generated accessor methods, forcing downstream code to hardcode spec values for asm operands and value construction. The new consts are a single source of truth, emitted once per logical field (getter side) so read-write fields get correctly-named consts (e.g. Mstatus::MIE_SHIFT) without duplication. The _SHIFT suffix matches the crate's existing convention (mconfigptr:: ALIGN_SHIFT, mvienh::INTERRUPT_SHIFT, mtval2::GUEST_PAGE_SHIFT) and the RISC-V C ecosystem (OpenSBI/Linux). Purely additive. Adds a doc(hidden) csr_field_consts! helper macro.
Build a trap-cause value from a CoreInterruptNumber or ExceptionNumber directly, setting the interrupt bit (via the macro-generated IS_INTERRUPT_MASK / INTERRUPT_MASK const) instead of hand-computing 1 << (XLEN-1). Named from_interrupt/from_exception because the scause `interrupt` field accessor already occupies Scause::interrupt.
The mstatus MIE/MPP/MPRV/... fields already get SHIFT/WIDTH/MASK consts from the field macros. UXL/SXL/SBE/MBE are implemented manually (RV64-only bits) and had no consts; add them additively so mstatus is fully covered. Existing accessor methods are left untouched.
Add BASE_SHIFT/BASE_MASK for the trap-vector base address field on Mtvec and Stvec. The MODE field already gets TRAP_MODE_SHIFT/WIDTH/MASK from the field macros. Purely additive; the private TRAP_MASK and address()/set_address() helpers are left untouched.
Add R/W/X permission bit consts, the PERMISSION (R/W/X) and A (addressing mode) sub-field shifts/widths/masks, and the L (locked) bit const to Pmp. PMP config uses the Permission/Range enums rather than the field macros, so these consts are defined manually. Additive; existing decoding in try_into_config untouched.
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This PR systematically adds associated constants for each bitfield in the CSRs. Most of the heavy
lifting was done by extending the existing bitfield definition macros (read_only_csr_field! /
read_write_csr_field!), but there were also specific additions for:
macros)
These are just new definitions, so no changes to existing APIs.