[executorch][cuda] Optimize short-query INT5 matvec kernels - #21505
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Pull Request resolved: #21473 Add compile-time M=2/3/4 fused short-query kernels while preserving the existing M=1 path. The shared ROWS template was reviewed and benchmarked by KernelAgent; KA found no faster safe rewrite, so the validated template is retained. A100 kernel microbenchmarks versus main: - M1: 0.10226 -> 0.10228 ms (performance neutral; no regression) - M2: 0.196 -> 0.127 ms (1.54x) - M3: 0.289 -> 0.159 ms (1.82x) - M4: 0.383 -> 0.196 ms (1.95x) Correctness tests cover M=1,2,3,4 with three randomized seeds. ptxas reports zero spills. ghstack-source-id: 408535989 @exported-using-ghexport Differential Revision: [D114032326](https://our.internmc.facebook.com/intern/diff/D114032326/)
Pull Request resolved: #21474 Add compile-time M=1/2/3/4 short-query paths and share their safe implementation through a ROWS/USE_SUM/GS16 device template. These kernels were generated and tuned with KernelAgent. Dispatch uses the regular gs16 kernels for M=1/2 and the precomputed-activation-sum kernels for M=3/4. The M=3 non-sum entry remains explicit as a performance/correctness comparison because templating that entry increased register pressure. A100 op-level results (N=6656, gs=16, three seeds): - M1, generic reference -> gs16: 0.039416 -> 0.038211 ms (1.032x; no regression) - M2, generic reference -> gs16: 0.055348 -> 0.032540 ms (1.701x) - M3, optimized non-sum -> activation-sum: 0.040003 -> 0.039949 ms (1.001x; neutral incremental change) - M4, generic reference -> activation-sum: 0.100204 -> 0.045694 ms (2.193x) The M3 baseline is intentionally the optimized non-sum kernel rather than the generic reference; this isolates the activation-sum optimization. All candidates are bitwise-correct across the three seeds, and ptxas reports zero spills. ghstack-source-id: 408539235 @exported-using-ghexport Differential Revision: [D114032330](https://our.internmc.facebook.com/intern/diff/D114032330/)
Pull Request resolved: #21475 Add specialized M=1 and M=4 short-query paths for the planar INT5 W5A8 matvec operator. These are the latency-sensitive single-row and four-row shapes. M=2/M=3 retain the generic fallback path; this change does not claim those shapes as optimized. The M=1 implementation shares safe gs32 decode/accumulate logic through a compile-time ROWS device template. M=4 remains explicit because KernelAgent experiments with the generalized template increased register pressure and regressed latency. The final kernels were generated and tuned with KernelAgent. A100 kernel microbenchmarks versus the previous generic path: - M1: 1.09971 -> 0.70441 ms (1.56x; no regression) - M4: 1.96445 -> 1.12976 ms (1.74x) - M2/M3: no specialized dispatch; generic fallback remains unchanged Correctness tests cover M=1,2,3,4 with three randomized seeds; ptxas reports zero spills. ghstack-source-id: 408539258 @exported-using-ghexport Differential Revision: [D114032323](https://our.internmc.facebook.com/intern/diff/D114032323/)
🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21505
Note: Links to docs will display an error until the docs builds have been completed. ❌ 1 New FailureAs of commit 561f006 with merge base 6898c99 ( NEW FAILURE - The following job has failed:
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This PR was created by the merge bot to help merge the original PR into the main branch.
ghstack PR number: #21475 by @Gasoonjia
^ Please use this as the source of truth for the PR details, comments, and reviews
ghstack PR base: https://github.com/pytorch/executorch/tree/gh/gasoonjia/180/base
ghstack PR head: https://github.com/pytorch/executorch/tree/gh/gasoonjia/180/head
Merge bot PR base: https://github.com/pytorch/executorch/tree/gh/gasoonjia/179/orig
Merge bot PR head: https://github.com/pytorch/executorch/tree/gh/gasoonjia/180/orig
Differential Revision: D114032323
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