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Merged
DanielKellerM merged 11 commits into from
Aug 12, 2026
Merged

Bump common_cells to v2 #99

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cd95fe3
Bump common_cells to v2
colluca Jun 16, 2026
490f1c8
Bump common cells to v2.0.0-beta
colluca Jul 3, 2026
55e3358
fix: Remove flush_i connection from i_rr_arb_tree
ricted98 Jul 7, 2026
512525e
hw: Complete common_cells v2 rename for devel-added instances
DanielKellerM Jul 10, 2026
2df5976
hw: Fix cc-v2 synth-pickle pragmas and desc64 usage_o widths
DanielKellerM Jul 28, 2026
17fc784
ci: Pin the nonfree ref to the common_cells v2 branch
DanielKellerM Jul 28, 2026
a2f2ffd
hw: Fix cc-v2 popcount output width in ND midend
DanielKellerM Jul 28, 2026
0d437a9
hw: Match desc64 idma_req_used width to cc-v2 usage_o exactly
DanielKellerM Jul 29, 2026
5e774dc
deps: Pin cc-v2 ecosystem dependencies to exact commits
DanielKellerM Jul 29, 2026
f8cbad4
test: Drop testmode_i from the MX TBs for the cc-v2 backend port list
DanielKellerM Aug 12, 2026
6755db0
deps: Repoint the axi pin at the reachable cc-v2 rev on devel
DanielKellerM Aug 12, 2026
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3 changes: 3 additions & 0 deletions .gitlab-ci.yml
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Expand Up @@ -5,6 +5,9 @@
# Authors:
# - Thomas Benz <tbenz@iis.ee.ethz.ch>

variables:
IDMA_NONFREE_COMMIT: common-cells-v2

default:
interruptible: true
hooks:
Expand Down
20 changes: 10 additions & 10 deletions Bender.lock
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@@ -1,30 +1,30 @@
packages:
apb:
revision: 77ddf073f194d44b9119949d2421be59789e69ae
version: 0.2.4
revision: 6a2bd0fe9f0822322104ac602fac5739fb063aa0
version: null
source:
Git: https://github.com/pulp-platform/apb.git
dependencies:
- common_cells
axi:
revision: a8c53cee2520d328d390c507c88818e8ac144c8c
version: 0.39.10
revision: 0ccc838fe06aeeb857eb83c6be9a915c4bf99566
version: null
source:
Git: https://github.com/pulp-platform/axi.git
dependencies:
- common_cells
- common_verification
- tech_cells_generic
axi_stream:
revision: 54891ff40455ca94a37641b9da4604647878cc07
version: 0.1.1
revision: 834639c9a39d00c063cef184164525416ef5b119
version: null
source:
Git: https://github.com/pulp-platform/axi_stream.git
dependencies:
- common_cells
common_cells:
revision: 1281545696eb3fcba50ec5b4275993476a3c710e
version: 1.40.0
revision: 03d98106aa19952a10360d2230def85144a0008b
version: 2.0.0-beta.2
source:
Git: https://github.com/pulp-platform/common_cells.git
dependencies:
Expand All @@ -37,8 +37,8 @@ packages:
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
obi:
revision: 0155fc34e900c7c884e081c0a1114a247937ff69
version: 0.1.7
revision: b69af4aa00630efd14b1c5cbf9bac977f23ce840
version: null
source:
Git: https://github.com/pulp-platform/obi.git
dependencies:
Expand Down
10 changes: 5 additions & 5 deletions Bender.yml
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Expand Up @@ -14,12 +14,12 @@ package:
- "Axel Vanoni <axvanoni@ethz.ch>"

dependencies:
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.9 }
axi_stream: { git: "https://github.com/pulp-platform/axi_stream.git", version: 0.1.1 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.39.0 }
axi: { git: "https://github.com/pulp-platform/axi.git", rev: 0ccc838fe06aeeb857eb83c6be9a915c4bf99566 }
axi_stream: { git: "https://github.com/pulp-platform/axi_stream.git", rev: 834639c9a39d00c063cef184164525416ef5b119 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 2.0.0-beta.2 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.5 }
apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 }
obi: { git: "https://github.com/pulp-platform/obi.git", version: 0.1.7 }
apb: { git: "https://github.com/pulp-platform/apb.git", rev: 6a2bd0fe9f0822322104ac602fac5739fb063aa0 }
obi: { git: "https://github.com/pulp-platform/obi.git", rev: b69af4aa00630efd14b1c5cbf9bac977f23ce840 }

export_include_dirs:
- src/include
Expand Down
2 changes: 1 addition & 1 deletion idma.mk
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Expand Up @@ -299,7 +299,7 @@ $(IDMA_FULL_TB): $(IDMA_TB_ALL)
.PHONY: idma_pickle_clean

IDMA_PICKLE_DIR := $(IDMA_ROOT)/target/pickle
IDMA_PICKLE_TARGETS := -t rtl -t synth -t asic -t snitch_cluster
IDMA_PICKLE_TARGETS := -t rtl -t synth -t asic -t snitch_cluster -t cc_no_deprecated
IDMA_PICKLE_ARGS ?=

$(IDMA_PICKLE_DIR)/%.sv: $(IDMA_BENDER_FILES) $(IDMA_FULL_TB) $(IDMA_FULL_RTL) $(IDMA_INCLUDE_ALL)
Expand Down
21 changes: 9 additions & 12 deletions src/backend/idma_channel_coupler.sv
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Expand Up @@ -28,8 +28,6 @@ module idma_channel_coupler #(
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
/// Testmode in
input logic testmode_i,

/// R response valid
input logic r_rsp_valid_i,
Expand Down Expand Up @@ -60,7 +58,7 @@ module idma_channel_coupler #(
);

/// The width of the credit counter keeping track of the transfers
localparam int unsigned CounterWidth = cf_math_pkg::idx_width(NumAxInFlight);
localparam int unsigned CounterWidth = cc_pkg::idx_width(NumAxInFlight);

/// Credit counter type
typedef logic [CounterWidth-1:0] cnt_t;
Expand Down Expand Up @@ -91,14 +89,14 @@ module idma_channel_coupler #(
assign first = r_rsp_valid_i & r_rsp_ready_i & r_rsp_first_i & !r_decouple_aw_i;

// stream fifo to hold AWs back
stream_fifo_optimal_wrap #(
cc_stream_fifo_optimal_wrap #(
.Depth ( NumAxInFlight ),
.type_t ( axi_aw_chan_t ),
.data_t ( axi_aw_chan_t ),
.PrintInfo ( PrintFifoInfo )
) i_aw_store (
.clk_i,
.rst_ni,
.testmode_i,
.clr_i ( 1'b0 ),
.flush_i ( 1'b0 ),
.usage_o ( /* NOT CONNECTED */ ),
.data_i ( aw_req_i ),
Expand All @@ -109,14 +107,14 @@ module idma_channel_coupler #(
.ready_i ( aw_ready )
);

stream_fifo_optimal_wrap #(
cc_stream_fifo_optimal_wrap #(
.Depth ( NumAxInFlight ),
.type_t ( logic ),
.data_t ( logic ),
.PrintInfo ( PrintFifoInfo )
) i_aw_decoupled_store (
.clk_i,
.rst_ni,
.testmode_i,
.clr_i ( 1'b0 ),
.flush_i ( 1'b0 ),
.usage_o ( /* NOT CONNECTED */ ),
.data_i ( aw_decouple_aw_i ),
Expand Down Expand Up @@ -160,12 +158,11 @@ module idma_channel_coupler #(

// fall through register to decouple the aw valid signal from the aw ready
// now payload is required; just the decoupling of the handshaking signals
fall_through_register #(
.T ( logic [0:0] )
cc_fall_through_register #(
.data_t ( logic [0:0] )
) i_fall_through_register_decouple_aw_valid (
.clk_i,
.rst_ni,
.testmode_i,
.clr_i ( 1'b0 ),
.valid_i ( aw_sent ),
.ready_o ( aw_ready_decoupled ),
Expand Down
7 changes: 3 additions & 4 deletions src/backend/idma_dataflow_element.sv
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Expand Up @@ -21,7 +21,6 @@ module idma_dataflow_element #(
)(
input logic clk_i,
input logic rst_ni,
input logic testmode_i,

input byte_t [StrbWidth-1:0] data_i,
input strb_t valid_i,
Expand All @@ -34,14 +33,14 @@ module idma_dataflow_element #(

// buffer is implemented as an array of FIFOs
for (genvar i = 0; i < StrbWidth; i++) begin : gen_fifo_buffer
passthrough_stream_fifo #(
.type_t ( byte_t ),
cc_passthrough_stream_fifo #(
.data_t ( byte_t ),
.Depth ( BufferDepth ),
.PrintInfo ( PrintFifoInfo )
) i_passthrough_stream_fifo (
.clk_i,
.rst_ni,
.testmode_i,
.clr_i ( 1'b0 ),
.flush_i ( 1'b0 ),
.data_i ( data_i [i] ),
.valid_i ( valid_i [i] ),
Expand Down
14 changes: 6 additions & 8 deletions src/backend/idma_error_handler.sv
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Expand Up @@ -33,8 +33,6 @@ module idma_error_handler #(
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
/// Testmode in
input logic testmode_i,

/// 1D iDMA response
output idma_rsp_t rsp_o,
Expand Down Expand Up @@ -136,14 +134,14 @@ module idma_error_handler #(
// FIFO: read address
// the read address FIFO is synchronized with the `i_w_last` FIFO in the backend. So at this
// point now full handshaking is required.
stream_fifo_optimal_wrap #(
cc_stream_fifo_optimal_wrap #(
.Depth ( MetaFifoDepth ),
.type_t ( addr_t ),
.data_t ( addr_t ),
.PrintInfo ( PrintFifoInfo )
) i_r_addr_store (
.clk_i,
.rst_ni,
.testmode_i,
.clr_i ( 1'b0 ),
.flush_i ( 1'b0 ),
.usage_o ( /* NOT CONNECTED */ ),
.data_i ( r_addr_i ),
Expand All @@ -157,14 +155,14 @@ module idma_error_handler #(
// FIFO: w address
// the read address FIFO is synchronized with the `i_w_last` FIFO in the backend. So at this
// point now full handshaking is required.
stream_fifo_optimal_wrap #(
cc_stream_fifo_optimal_wrap #(
.Depth ( MetaFifoDepth ),
.type_t ( addr_t ),
.data_t ( addr_t ),
.PrintInfo ( PrintFifoInfo )
) i_w_addr_store (
.clk_i,
.rst_ni,
.testmode_i,
.clr_i ( 1'b0 ),
.flush_i ( 1'b0 ),
.usage_o ( /* NOT CONNECTED */ ),
.data_i ( w_addr_i ),
Expand Down
48 changes: 21 additions & 27 deletions src/backend/tpl/idma_backend.sv.tpl
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Expand Up @@ -106,8 +106,6 @@ module idma_backend_${name_uniqueifier} #(
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
/// Testmode in
input logic testmode_i,

/// 1D iDMA request
input idma_req_t idma_req_i,
Expand Down Expand Up @@ -508,11 +506,12 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i,
end else begin : gen_no_hw_legalizer
// stream fork is used to synchronize the two decoupled channels without the need for a
// FIFO here.
stream_fork #(
.N_OUP ( 32'd2 )
cc_stream_fork #(
.NumOup ( 32'd2 )
) i_stream_fork (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clr_i ( 1'b0 ),
.valid_i ( req_valid_leg ),
.ready_o ( leg_ready ),
.valid_o ( { r_valid, w_valid } ),
Expand Down Expand Up @@ -582,7 +581,6 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i,
) i_idma_error_handler (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( testmode_i ),
.rsp_o ( idma_rsp ),
.rsp_valid_o ( rsp_valid ),
.rsp_ready_i ( rsp_ready ),
Expand Down Expand Up @@ -652,14 +650,14 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i,
//--------------------------------------
// Datapath decoupling
//--------------------------------------
stream_fifo_optimal_wrap #(
cc_stream_fifo_optimal_wrap #(
.Depth ( NumAxInFlight ),
.type_t ( r_dp_req_t ),
.data_t ( r_dp_req_t ),
.PrintInfo ( PrintFifoInfo )
) i_r_dp_req (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( testmode_i ),
.clr_i ( 1'b0 ),
.flush_i ( 1'b0 ),
.usage_o ( /* NOT CONNECTED */ ),
.data_i ( r_req.r_dp_req ),
Expand All @@ -670,14 +668,14 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i,
.ready_i ( r_dp_req_out_ready )
);

stream_fifo_optimal_wrap #(
cc_stream_fifo_optimal_wrap #(
.Depth ( NumAxInFlight + ComputeFifoDepth ),
.type_t ( w_dp_req_t ),
.data_t ( w_dp_req_t ),
.PrintInfo ( PrintFifoInfo )
) i_w_dp_req (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( testmode_i ),
.clr_i ( 1'b0 ),
.flush_i ( 1'b0 ),
.usage_o ( /* NOT CONNECTED */ ),
.data_i ( w_req.w_dp_req ),
Expand All @@ -698,8 +696,8 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i,
end
% endif

fall_through_register #(
.T (\
cc_fall_through_register #(
.data_t (\
% if one_read_port:
read_meta_channel_t\
% else:
Expand All @@ -709,7 +707,6 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i,
) i_ar_fall_through_register (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( testmode_i ),
.clr_i ( 1'b0 ),
.valid_i ( r_valid ),
.ready_o ( ar_ready ),
Expand All @@ -729,14 +726,14 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i,
//--------------------------------------
// Last flag store
//--------------------------------------
stream_fifo_optimal_wrap #(
cc_stream_fifo_optimal_wrap #(
.Depth ( MetaFifoDepth ),
.type_t ( logic [1:0] ),
.data_t ( logic [1:0] ),
.PrintInfo ( PrintFifoInfo )
) i_w_last (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( testmode_i ),
.clr_i ( 1'b0 ),
.flush_i ( 1'b0 ),
.usage_o ( /* NOT CONNECTED */ ),
.data_i ( {w_req.super_last, w_req.last} ),
Expand Down Expand Up @@ -797,8 +794,7 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i,

) i_idma_transport_layer (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( testmode_i )\
.rst_ni ( rst_ni )\
% for protocol in used_read_protocols:
,
% if database[protocol]['passive_req'] == 'true':
Expand Down Expand Up @@ -870,7 +866,6 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i,
) i_idma_channel_coupler (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( testmode_i ),
.r_rsp_valid_i ( r_chan_valid ),
.r_rsp_ready_i ( r_chan_ready ),
.r_rsp_first_i ( r_dp_rsp.first ),
Expand Down Expand Up @@ -913,15 +908,15 @@ w_req.decouple_aw || (w_req.w_dp_req.dst_protocol inside {\
% if combined_aw_and_w:
% if compute_eligible:
// combined aw+w read-meta buffer; deepened for the compute engine tile read-ahead (cf. i_w_dp_req)
stream_fifo_optimal_wrap #(
cc_stream_fifo_optimal_wrap #(
.Depth ( EnableCompute ? NumAxInFlight + ComputeFifoDepth : 32'd2 ),
% else:
// Atleast one write protocol uses combined aw and w -> Need to buffer read meta requests
// As a write could depend on up to two reads
stream_fifo_optimal_wrap #(
cc_stream_fifo_optimal_wrap #(
.Depth ( 2 ),
% endif
.type_t (\
.data_t (\
% if one_write_port:
write_meta_channel_t ),
% else:
Expand All @@ -931,7 +926,7 @@ w_req.decouple_aw || (w_req.w_dp_req.dst_protocol inside {\
) i_aw_fifo (
.clk_i,
.rst_ni,
.testmode_i,
.clr_i ( 1'b0 ),
.flush_i ( 1'b0 ),
.usage_o ( /* NOT CONNECTED */ ),
.data_i ( \
Expand All @@ -949,8 +944,8 @@ w_req.decouple_aw || (w_req.w_dp_req.dst_protocol inside {\
% else:
// Add fall-through register to allow the input to be ready if the output is not. This
// does not add a cycle of delay
fall_through_register #(
.T (\
cc_fall_through_register #(
.data_t (\
% if one_write_port:
write_meta_channel_t )
% else:
Expand All @@ -959,7 +954,6 @@ w_req.decouple_aw || (w_req.w_dp_req.dst_protocol inside {\
) i_aw_fall_through_register (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( testmode_i ),
.clr_i ( 1'b0 ),
.valid_i ( w_valid ),
.ready_o ( aw_ready ),
Expand Down
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