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Fix performance and functional issues in cache controller - #59
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🔵 Needs a closer look
Changes to dirty-line flush sequencing and writeback backpressure require RTL simulation to verify data integrity, forward progress, and the re-enabled timing assertion, but simulation was unavailable in this review.
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What changed in this PR
This PR updates the cache-controller dependency to address the reported hashing bug and restores enforcement of the previously waived L1 bypass timing check.
Changes:
- Advances the
insitu-cachedependency revision. - Makes the bypass-disabled timing check report and count failures instead of waiving them.
| File | Description |
|---|---|
software/tests/l1-bypass/main.c |
Restores failure reporting and counting for the bypass-disabled timing check. |
Bender.lock |
Pins insitu-cache to the revision intended to fix the cache-controller issues. |
Review effort: Balanced
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Fix a bug in the controller's hashing function, which caused a previous test case to fail.