[luca24balboni]

This PR reworks the memory map of the tile so that every byte of physical memory has exactly one address, and lays out the program contiguously in L2.

Address map

Before, scratch and stacks were an alias over the bottom of tile 0's window, and the tile peripherals covered the first 14 KiB of the L1, which therefore had no usable address.

• Tile peripherals move to fixed offsets from 0xA000_0000, outside the tile windows; resizing or removing one unit no longer moves the others.
• The private part of the L1 (TileCfg.L1.PrivBytes) gets its own view at 0xA010_0000, the same address in every tile.
• The global part stays in the tile window, at k * 0x0010_0000 + PrivBytes. The window stays 1 MiB, so a tile can instantiate a smaller L1.

Memory sizes

• L1: 1 MiB (32 banks x 8192 words), of which 128 KiB private and 896 KiB global.
• Control-core I$: 2 KiB, 4 ways. PULP cluster I$ (4 KiB shared) and Spatz I$ (2 KiB) unchanged.

Software layout

• L2 is contiguous from 0xC000_0000: code (32 KiB), exit codes, then the program data.
• Stacks are packed at the top of the private L1; the scratch takes the rest.
• Linker scripts, crt0, magia_tile_utils.h, the testbench VIPs and s19tomem.py follow the new addresses.

Docs

New memory map and software layout figures, and address tables in the README.

[yvantor]

@luca24balboni is this tracked with an issue?

[luca24balboni]

No, it comes from a discussion on the group, but there are no issues on this on the Dashboard, I'm opening it