[luca24balboni]

Summary

This PR replaces the local interconnect of magia_isle and makes the arbitration between accelerators and cores configurable from software. It also lets RedMulE access the TCDM at misaligned addresses.

New interconnect:
magia_hci_interconnect replaces local_interconnect, and HCI moves to 2.6.1.

Configurable arbitration:
A new control register (obi_slave_ctrl_hci) sets how the interconnect arbitrates between the wide side (RedMulE and iDMA) and the narrow side (cores).
It controls which side has priority and a programmable priority ratio.
At reset the policy is a fair 1:2 round-robin.

RedMulE misaligned access:
RedMulE can now access the TCDM at addresses that are not aligned to a bank word.
The new TileCfg.RedMule.MisalignedAccess enables it, and it is on by default.
When it is on, the RedMulE HCI port is one bank word (32 bit) wider, so it uses one more bank on the interconnect.

Tests and SW
New magia_stats.h, which now holds the cycle and time counter helpers previously in magia_tile_utils.h.
New test hci_arb_redmule_bench: a RedMulE run under the different arbitration policies.
matmul_compare_spatz_test updated.

[FrancescoConti]

Ciao, I will look at the code in more detail but one thign that I think should go here is the support for misaligned access in RedMulE. I thought we had that already, but it's disabled.

Claudio-generated instructions to enable it (I did not check the specific lines of code but generally speaking they check out):

1. hw/tile/magia_redmule_wrap.sv
   • Add the parameter parameter int unsigned MisalignedAccessSupport = 1.
   • Change the default tcdm width from DW: DataW to DW: DataW + (MisalignedAccessSupport ? 32 : 0).
   • Pass .MisalignedAccessSupport ( MisalignedAccessSupport ) to redmule_top.
   • Keep the EXPECTED_DATAW check on DataW as it is: DataW stays the systolic-array width, which is what redmule_tiler checks.
2. hw/tile/magia_isle.sv, lines 144–147: add localparam int unsigned RedmuleHciW = RedmuleDataW + 32;. Use it for the data width and the strobe width (RedmuleHciW/BWH) of tile_redmule_data_req_t and tile_redmule_data_rsp_t.
3. hw/tile/magia_isle.sv, line 1228: change HCI_SIZE_PARAM(hci_redmule_if) from DW: RedmuleDataW to DW: RedmuleHciW.
4. hw/tile/magia_isle.sv, around line 1665 (i_redmule_wrap): pass .MisalignedAccessSupport ( 1 ).
   • Keep .DataW ( RedmuleDataW ).
   • HCI_SIZE_PARAM(tcdm) already comes from hci_redmule_if, so it follows step 3.
   • The gen_no_redmule branch uses the same types and needs no change.

Maybe instead of defaulting to 1 we can expose this in a package parameter (with default 1 - I really see no reason to not support misaligned access).

[yvantor]

Addressing #91