fix: select precise M=16 verify kernel on M1

[aunali1]

Summary

• route M1 M=16 auto-selection through the FP32-accumulating combo kernel
• preserve the existing selector policy on non-M1 GPUs, including the G17 NAX path
• pin G13 fingerprints for the existing M=16 and M=4 production shapes
• document the architecture-specific auto-selection behavior

Root cause

The M=16 FP16 tree stores each simdgroup partial in FP16 before the final FP32 reduction. On applegpu_g13s, that produces a repeatable one-BF16-ULP error at the planted gate/up logit: maximum deviation was 0.0078125 for all three contract seeds, above the existing 0.001 bound.

The pre-existing combo kernel keeps the matrix accumulation and cross-simdgroup reduction in FP32. Its maximum deviation was 0.000122070, 0.000122070, and 0.000244141 across the same seeds, with all margin-certified argmaxes preserved.

Performance

On an Apple M1 Max, the isolated 16x5120x17408 product-shape kernel benchmark measured 90 synchronized runs per path:

• previous FP16 tree median: 1.893625 ms
• M1 combo auto-path median: 1.112480 ms
• latency reduction: 41.3%

This is an M=16 kernel result. The Qwen3.8 DFlash2 checkpoint is native M=8 and does not exercise this path.

Validation

• pytest -q tests/test_verify_kernel_contract.py: 12 passed
• pytest -q tests/test_verify_kernel_contract.py tests/test_verify_qmm_parity.py -k m16: 9 passed, 2 skipped
• full suite: 1323 passed, 14 skipped
• git diff --check: clean