FPGA Stream Processor

A self-directed Verilog project for simple streaming-style data processing in RTL.

The project implements a simple message processing pipeline that parses fixed-width input messages, applies filtering rules, and produces an output decision. It is a learning project about RTL design, simulation and verifying hardware designs against a software reference model.

flowchart LR
    A("32-bit message<br/>input_valid") --> B["input register<br/>(clk, reset)"]
    B --> C["parser / filter / formatter"]
    C --> D["output register<br/>(clk, reset)"]
    D --> E("value_a / value_b<br/>reject_reason<br/>output_valid")

Loading

For flowchart with module-level detail, see rtl/README.md.

Current Features

• Synchronous Verilog message-processing pipeline
• 32-bit parser, parameterised filter, and output formatter
• cocotb verification with fixed and randomised test cases
• Python reference model for expected behaviour
• GitHub Actions CI for automated tests
• Vivado synthesis and timing reports

Message Format

Bits	Field	Width
31:28	message_type	4 bits
27:24	channel_id	4 bits
23:16	value_a	8 bits
15:8	value_b	8 bits
7:0	flags	8 bits

Verification

The project currently includes fixed-case and randomised cocotb tests. The cocotb randomised tests run automatically using GitHub Actions.

For cocotb setup and test-running instructions, see tb/cocotb/README.md.

File	Purpose
test_direct_cases.py	Fixed input cases with manually specified expected outputs
test_reference_cases.py	Fixed input cases checked against Python reference model
test_random_reference.py	Randomised input cases checked against Python reference model
reference_model.py	Python software model of the expected RTL behaviour

Vivado synthesis and timing reports are included in docs/synthesis.md.

Example cocotb Output:

   210.00ns INFO     cocotb.regression                  test_direct_cases.fixed_direct_cases passed
   430.00ns INFO     cocotb.regression                  test_reference_cases.fixed_reference_cases passed
300450.00ns INFO     test                               10000 tests ran successfully...
300450.00ns INFO     cocotb.regression                  test_random_reference.random_reference_cases passed


** TEST                                          STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
** test_direct_cases.fixed_direct_cases           PASS         210.00           0.00     105434.98  **
** test_reference_cases.fixed_reference_cases     PASS         220.00           0.00     126716.13  **
** test_random_reference.random_reference_cases   PASS      300020.00           1.17     257507.56  **
** TESTS=3 PASS=3 FAIL=0 SKIP=0                             300450.00           1.22     245419.42  **

Status

Synchronous RTL pipeline is implemented and verified with fixed and randomised cocotb tests against a Python reference model. Vivado synthesis and post-synthesis timing checks have also been run for the current design.