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[DSLX] Support aliased state types and channel arrays in impl-style procs. - #5146
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…rocs. Converting legacy procs to impl-style syntax fails when a proc's state type is a type alias over a constant-sized array or when a proc declares channel arrays. Type unification against the built-in proc state wrapper evaluates array dimensions in the built-in stubs module rather than the user module, causing a span validation failure when the dimension references a user-defined constant. Additionally, constexpr evaluation and IR conversion of impl-style proc constructors assume scalar channel declarations and drop caller parametric bindings, causing crashes on channel arrays and parametric proc hierarchies. Evaluate type alias targets in their defining module during type reference unification, generalize constexpr channel creation and IR channel array expansion to handle arbitrary array dimensions while preserving caller parametric bindings, and include impl-style procs when resolving top-level Verilog generation entries. This unblocks converting the memory_proc and matmul_4x4 examples to impl-style proc syntax. PiperOrigin-RevId: 1008013383
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[DSLX] Support aliased state types and channel arrays in impl-style procs.
Converting legacy procs to impl-style syntax fails when a proc's state type is a type alias over a constant-sized array or when a proc declares channel arrays. Type unification against the built-in proc state wrapper evaluates array dimensions in the built-in stubs module rather than the user module, causing a span validation failure when the dimension references a user-defined constant. Additionally, constexpr evaluation and IR conversion of impl-style proc constructors assume scalar channel declarations and drop caller parametric bindings, causing crashes on channel arrays and parametric proc hierarchies.
Evaluate type alias targets in their defining module during type reference unification, generalize constexpr channel creation and IR channel array expansion to handle arbitrary array dimensions while preserving caller parametric bindings, and include impl-style procs when resolving top-level Verilog generation entries. This unblocks converting the memory_proc and matmul_4x4 examples to impl-style proc syntax.