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1. hkust-zhiyao/MasterRTL hkust-zhiyao/MasterRTL Public

   MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

   Verilog 73 15

2. hkust-zhiyao/AssertLLM hkust-zhiyao/AssertLLM Public

   Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs

   Verilog 64 9

3. hkust-zhiyao/RTL-Timer hkust-zhiyao/RTL-Timer Public

   Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization

   Verilog 44 8

4. hkust-zhiyao/CircuitFusion hkust-zhiyao/CircuitFusion Public

   CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)

   Python 41 6

5. hkust-zhiyao/NetTAG hkust-zhiyao/NetTAG Public

   NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)

   Verilog 25 1

6. hkust-zhiyao/DR_RTL hkust-zhiyao/DR_RTL Public

   Dr.RTL: Autonomous Agentic RTL optimization through Tool-Grounded Self-Improvement

   Verilog 22 5