feat(process): vcad-process — planar TCAD-lite process simulation#395
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New vcad-process crate: GDS masks + a serializable process recipe (Deposit, PatternEtch, GrowOxide with 0.46 Si consumption, Implant, Planarize) run through a planar film-stack simulator built on geo boolean ops. Emits vcad-ir documents in the gdsii-bridge sketch+extrude style: simulate_3d for a windowed die film stack, cross_section for the textbook process cross-section with exact per-interval gaps where material was etched. Includes a sky130-ish end-to-end example over the haiku_gen die. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
New ProcessSteps: SpinResist (positive/negative tone film on the top surface), Expose (records pattern + dose on the resist; dose is bookkeeping until dose-to-clear lands), Develop (tone-aware boolean on the resist footprint), EtchThroughResist (etches the film below where resist is absent — the physically honest PatternEtch), and Strip. Resist films carry a public ResistState, render as classic amber in both emitters, and the full spin→expose→develop→etch→strip sequence is tested to land on geometry identical to the idealized PatternEtch for both tones. PatternEtch itself is unchanged (now sharing an etch_film helper for the through/partial split). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
…ble sections Real film stacks are ~7 um tall on cuts hundreds of um long — a ribbon at true aspect. z_scale multiplies each film's z-extent at emission only; simulation footprints and thickness math stay physical. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
What shippedYou can now simulate a semiconductor fabrication process directly from a chip layout file. Give the tool a layout and a process recipe — describing steps like depositing films, etching patterns, growing oxide, implanting dopants, and planarizing — and it produces two outputs:
Recipes are plain, readable files that can be saved alongside the layouts they describe, and the full photolithography sequence (spin coat, expose, develop, etch, strip) is now supported as an alternative to the simplified one-step etch shortcut. Plain-English summary generated by Choji from this pull request. |
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What
New
vcad-processcrate: planar ("TCAD-lite") semiconductor process simulation — the digital twin of a fab, and M2 of the chip-design arc that produced vcad-gdsii (#387/#394).Deposit,PatternEtch,GrowOxide(0.46 Si-consumption rule),Implant,Planarizeover a substrate.SpinResist(positive/negative tone),Expose(mask layer + dose),Develop,EtchThroughResist,Strip— with an equivalence test proving the full litho sequence reproduces the idealizedPatternEtchfilm-by-film (both tones/polarities). Resist renders amber while present.vcad-gdsii::flatten+ pure-Rustgeobooleans, clipped to the region of interest before any boolean so full-die cuts stay cheap.vcad_ir::Document:simulate_3d(windowed 3D film stack) andcross_section/cross_section_scaled(textbook cut with exact analytic interval extraction; etched-away intervals genuinely absent; optional vertical exaggeration).Validated against a real librelane sky130 die (haiku_gen): the cross-section shows implant wells under field-oxide openings, poly, li1, met1/met2 with correct gaps.
Testing
35 tests: interval extraction (holes → gaps, span clipping, Y cuts, merging), etch subtraction, GrowOxide consumption math, Planarize, implant inset, mask clipping/union, window crop, resist tone semantics, litho↔PatternEtch equivalence, z-scale emission, serde round-trips, bad-input rejection. Clippy
-D warnings+ fmt clean.Known planar-v0 limitations documented in the README (scalar top surface — no conformal deposition, anisotropic etch only, box implants, blanket oxidation).
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