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Achievement: Pull Shark

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Achievement: Pull Shark

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destinyN1/README.md

Electrical and Electronic Engineering Graduate

Professional Summary

Electrical and Electronic Engineering graduate seeking opportunities in software development and digital hardware design. Interested in roles that leverage both software expertise and hardware knowledge.

Areas of Interest

Hardware Design

  • ASIC Design
  • FPGA Development

Software Development

  • Embedded Systems
  • General Software Engineering

Core Technical Competencies

Primary Languages

  • C and Embedded C
  • Python
  • SystemVerilog

Additional Languages

  • ARM Assembly
  • VHDL

Scripting & Automation

  • C-Shell (csh) for scripting and automation workflows

Projects

My most significant technical achievement to date is my ChaCha20 and Poly1305 ASIC project it remains incomplete due to unforeseen circumstances, it represents substantial work in cryptographic hardware implementation and stands as my proudest technical undertaking.

Additional projects and work can be explored throughout my repositories.

Personal Interests

I maintain commited to continuous learning through self-study of medical literature, physics, and mathematics. Outside of technical pursuits, I enjoy playing music and maintaining an active lifestyle through fitness training.

Contact

Open to discussing opportunities in embedded systems, software engineering, and digital hardware design.

You can reach me at destinynewman79@gmail.com

Pinned Loading

  1. Open-Source-ChaCha20-Poly1305_AEAD-Engine_RTL---GDSII-Flow Open-Source-ChaCha20-Poly1305_AEAD-Engine_RTL---GDSII-Flow Public

    SystemVerilog 1

  2. PC-screen-time-tracker PC-screen-time-tracker Public

    Python

  3. AHB-Lite-Bus-Protocol-With-Central-Arbitration AHB-Lite-Bus-Protocol-With-Central-Arbitration Public

    This project implements an **AHB-Lite Arbiter** and Several IPs using VHDL, featuring a round-robin arbitration mechanism for efficient bus access among multiple masters (I2C, SPI, CCP, UART, SSI, …

    VHDL

  4. JTAG-Finite-State-Machine JTAG-Finite-State-Machine Public

    The JTAG_FSM project implements a JTAG (Joint Test Action Group) Finite State Machine in VHDL, adhering to the IEEE standard for JTAG operations. This FSM facilitates testing and debugging of digit…

    VHDL

  5. 3rd-Year-Project 3rd-Year-Project Public

    Ball Balancing plate using PID controller to control 2 servo motors and a 5-pin capacitative touch plate. Implemented all in Arduino

    C++ 1

  6. pycpp-indicator-engine pycpp-indicator-engine Public

    Python 1