STANN-AIEML

STANN-AIEML (Synthesis Template for Artificial Neural Network on AI Engine-ML) is an end-to-end hardware–software co-design framework for deploying deep neural networks on AMD Versal AI Edge devices featuring AI Engine-ML (AIE-ML) accelerators.

Built upon the original STANN framework, STANN-AIEML extends its capabilities by supporting AI Engine-based neural network inference, automatic code generation, configurable hardware parallelism, and heterogeneous execution across the Processing System (PS), Programmable Logic (PL), and AI Engine (AIE-ML).

The framework enables researchers and developers to transform trained neural network models into efficient FPGA implementations with minimal manual effort. It automatically generates AI Engine kernels, graph descriptions, programmable logic kernels, host applications, and build configurations compatible with the AMD Vitis toolchain.

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Features

• End-to-end neural network deployment on AMD Versal AI Edge devices

• Native support for AI Engine-ML (AIE-ML)

• Automatic code generation for

  • AI Engine kernels
  • Graph API
  • Programmable Logic (PL) kernels
  • Host applications
  • Hardware Link file

• Support for multiple numerical precisions

  • bfloat16
  • float

• Configurable hardware parallelism

  • Processing Elements (PEs)
  • SIMD vectorization
  • Layer-level parallelism

• Optimized data movement between PS, PL, and AI Engine

• Template-based C++ implementation for high extensibility

• Modular layer library for rapid development of new operators

• Publications

If you use STANN-AIEML in your research, please cite the associated publication.

@inproceedings{li2026high,
  author    = {Yu Li and Mario Porrmann},
  title     = {{High Performance Implementation of Convolutional Neural Networks on Versal AI Engine with STANN-AIEML}},
  booktitle = {39th {GI/ITG} International Conference on Architecture of Computing Systems ({ARCS} 2026)},
  address   = {Mainz, Germany},
  month     = {March},
  year      = {2026}
}

One accelerator based on STANN-AIEML for direct arc fault detection is published in the following paper.

@InProceedings{10.1007/978-3-032-29365-7_2,
author="Li, Yu
and Mao, Yufei
and Weiss, Roland
and Porrmann, Mario",
editor="Leone, Gianluca
and Otero, Andr{\'e}s
and Busia, Paola
and Meloni, Paolo",
title={{High Performance Convolutional Neural Network Acceleration on Versal AI Edge Devices for Real Time DC Series Arc Fault Detection}},
booktitle="Applied Reconfigurable Computing. Architectures, Tools, and Applications",
year="2027",
publisher="Springer Nature Switzerland",
address="Cham",
pages="16--33",
abstract="Direct current (DC) series arc fault detection is a critical task in electrical safety systems, demanding high detection accuracy, low inference latency, and energy efficiency. Convolutional neural networks (CNNs) have shown strong potential for identifying arc fault patterns. However, their efficient deployment on embedded hardware platforms remains an open research challenge. The AI Engine--Machine Learning (AIE-ML), an ML-optimized variant of the AI Engine array in Versal adaptive SoCs, is well suited to these requirements, offering a programmable, vector-centric compute fabric tailored to the constraints of edge devices. To fully exploit this architecture, we develop STANN-AIEML, an open-source hardware--software co-design workflow that enables efficient inference of deep learning models on the Versal AI Edge platforms. The proposed framework streamlines the mapping and optimization of neural networks onto AIE-ML-based architectures, facilitating high-performance and rapid deployments in resource-constrained environments.",
isbn="978-3-032-29365-7",
note={DOI: \url{https://doi.org/10.1007/978-3-032-29365-7_2}}
}

STANN-AIEML aims to simplify the deployment of deep neural networks on AMD Versal AI Edge platforms by providing an automated, configurable, and extensible hardware–software co-design framework for AI Engine-ML accelerators.