Name		Name	Last commit message	Last commit date
CPU_Project.board/minized		CPU_Project.board/minized
CPU_Project.cache/wt		CPU_Project.cache/wt
CPU_Project.gen/sources_1/bd		CPU_Project.gen/sources_1/bd
CPU_Project.hw/hw_1		CPU_Project.hw/hw_1
CPU_Project.ip_user_files		CPU_Project.ip_user_files
CPU_Project.srcs		CPU_Project.srcs
CPU_Project		CPU_Project
microcontroller		microcontroller
.gitignore		.gitignore
CPU_Project.xpr		CPU_Project.xpr
README.md		README.md
REFACTOR_SUMMARY.md		REFACTOR_SUMMARY.md
archive_project_summary.txt		archive_project_summary.txt
vivado.jou		vivado.jou
vivado_16104.backup.jou		vivado_16104.backup.jou

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Microcontroller

1 clock cycle microcontroller in Verilog TODO: remake whole repo

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1 clock cycle microcontroller in Verilog

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