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arch/risc-v/eic7700x: Add the CLMM pad multiplexer. - #20063

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arch/risc-v/eic7700x: Add the CLMM pad multiplexer.#20063
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Summary

Every ball on the EIC7700X is shared between several functions, and nothing in
this port could see which function a pad carried or change it. This registers
the Chip Level Mode Mux with the pinctrl framework, describes all 166 pads and
every documented function select, and lists them in /proc/pinctrl.

It is the first pinctrl provider in the tree: the framework's read-back landed
in #19871 with nothing implementing it until now.

  • arch: Describe and configure the pads.: the provider and the pad tables
  • boards: Report the pads at startup.: one line of boot output
  • arch: Describe the pads through procfs.: get_pad, so pads carry names
  • boards: Enable the pinctrl procfs entry.: the two board configurations

The pad tables carry the judgement calls, each recorded with its TRM citation at
the row or function it applies to: which bits the manual says are writable, the
three pads this driver refuses to move, the pads whose documented functions are
a subset of what the field can hold, and the two balls that have no pad register
at all. Initialisation writes nothing to the hardware.

Output

[CPU0] pinctrl: 166 pads, 3 configured

/proc/pinctrl, abridged from 166 rows:

pinctrl0: 166 pads
0    CHIP_MODE            func:0 sel:CHIP_MODE        ds:0 pu:0 pd:1 ie:1 smt:1 slew:-
5    XIN                  func:- sel:-                ds:12 pu:- pd:- ie:- smt:- slew:- frs:2 rd:0
103  UART0_TX             func:0 sel:UART0_TX         ds:1 pu:0 pd:0 ie:0 smt:0 slew:-
139  GPIO92               func:0 sel:I2C8_SCL         ds:1 pu:0 pd:0 ie:1 smt:0 slew:-
141  S_MODE               func:2 sel:GPIO94           ds:1 pu:0 pd:1 ie:0 smt:0 slew:-
163  LPDDR_REF_CLK        func:- sel:-                ds:0 pu:0 pd:0 ie:1 smt:0 slew:- ms:3
164  ADDR_RGMII0_SEL_MODE func:- sel:-                ds:- pu:- pd:- ie:- smt:- slew:- ms1:1 ms2:1

Every line carries the same tokens, with - where the pad's layout has no such
field, so the file parses without knowing pad shapes. Names are the manual's and
describe a pad's default function, not its current one, which is why pad 141 is
S_MODE while sel: reads GPIO94. The name table costs about 9 KiB and is
built only when something will print it.

Testing

Booted on the ESWIN EIC7700 EVB, TFTP loaded from U-Boot, /proc/pinctrl read
back in full: ids 0 to 165, no gaps or repeats.

Compiled with -Wno-cpp -Werror. tools/checkpatch.sh -c -u -m -g master..HEAD
passes.

CONFIG_PINCTRL_PROCFS depends on FS_PROCFS_REGISTER, so both board
configurations enable it; without it the symbol is dropped when the
configuration is regenerated and the entry never appears.

Every ball on this SoC is shared between several functions, and nothing
in this port could see which function a pad carried or change it.  A
driver that finds nothing cannot tell a dead block from a pad still
pointed somewhere else.

Registers the CLMM pad multiplexer with the pinctrl framework and defines
every pad and every function select the manual documents, across the
straps, JTAG, PCIe, HDMI, Ethernet, I2S, SPI, GPIO, USB, I2C, UART, fan
and MIPI CSI groups.  Writes nothing at start up: a pad only moves when a
driver asks.

eic7700x_pinctrl_count() reports how many pads currently differ from
their reset defaults, which after boot is the set the boot loader and the
drivers have configured; the board start up logs it.

Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
Log one line from board start up with the pad count and how many differ
from their reset defaults, through eic7700x_pinctrl_count().  A helper
holds its locals so nothing stays on the stack for the bring up that
follows.

Turn the pinctrl driver's error output on for both boards, so a refused
pad write says why rather than merely failing.

Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
Implements the pinctrl get_pad method, so /proc/pinctrl and
PINCTRLC_GETPAD carry what this block is actually holding: each layout's
common fields with their validity bits, and the layout's own fields, the
RGMII and mode-select voltage bits and the oscillator tuning, as
key:value text.

Names every pad and every documented function select in one
PINCTRL_PADNAME() table, so func:2 on S_MODE reads as GPIO94 rather than
as a number.  The names are the manual's own; a pad's name describes its
default function, not its current one.  The table costs about 9 KiB and
is built only with the file that reads it; the name helpers return NULL
without it and the strings stay empty.

Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
Publishes /proc/pinctrl on both boards, which lists every pad with the
function it currently carries.  The startup banner counts how many pads
differ from their reset values, once, at boot; this answers the same
question at any later moment, which is what is wanted when a driver has
just reconfigured a pad and the result is not what was expected.

PINCTRL_PROCFS depends on FS_PROCFS_REGISTER, the entry registering
itself at run time rather than being one of the built in ones.  Neither
board set it, and without it the symbol is dropped when the configuration
is regenerated and the entry never appears, which is silent: the
defconfig still reads as though the feature were on.

Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
@Fishwaldo
Fishwaldo requested a review from lupyuen as a code owner September 6, 2026 11:17
@github-actions github-actions Bot added Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. Board: risc-v labels Sep 6, 2026
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github-actions Bot commented Sep 6, 2026

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MemBrowse Memory Report

No memory changes detected for:

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Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Board: risc-v Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces.

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