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arch/atomic: remove up_testset in spinlock - #20056

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xiaoxiang781216 merged 1 commit into
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zhangyu-duck:arch-atomic-remove-up_testset
Sep 8, 2026
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arch/atomic: remove up_testset in spinlock#20056
xiaoxiang781216 merged 1 commit into
apache:masterfrom
zhangyu-duck:arch-atomic-remove-up_testset

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@zhangyu-duck zhangyu-duck commented Sep 4, 2026

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Summary

Remove the per-arch testset implementation from the spinlock layer. The testset abstraction predates the unified spinlock.h API and is no longer used now that all arches provide spin_lock_irqsave()/spin_unlock_irqrestore() directly.

Changes

  • Delete arch/<arch>/include/spinlock.h and the per-arch *_testset.{c,S} implementations for arm, sim, sparc, tricore, x86_64, xtensa
  • Drop the CXD56_TESTSET, CXD56_TESTSET_WITH_HWSEM, and CXD56_ATOMIC_WITH_HWSEM Kconfig options from arch/arm/src/cxd56xx/Kconfig
  • Simplify the CXD56 semaphore pool loop in cxd56_sph.c to a single for (i = 3; i < 15; i++) path
  • Clean up the SMP/testset references in Documentation/

Impact

  • Archs that previously relied on testset for spinlock must now provide spin_lock_irqsave()/spin_unlock_irqrestore() via arch/<arch>/include/spinlock.h (or the default up_irq_save()/up_irq_restore() fallback in include/nuttx/spinlock.h). All currently-supported arches already do this.
  • CXD56 no longer exposes the custom testset/hwsem config knobs; its spinlock path falls back to the generic IRQ-based implementation.
  • No functional change for arches that were already using the unified spinlock API.

@github-actions github-actions Bot added Area: Documentation Improvements or additions to documentation Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: ceva Issues related to CEVA architecture Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: tricore Issues related to the TriCore architecture from Infineon Arch: x86_64 Issues related to the x86_64 architecture Arch: xtensa Issues related to the Xtensa architecture Size: M The size of the change in this PR is medium labels Sep 4, 2026
@zhangyu-duck
zhangyu-duck force-pushed the arch-atomic-remove-up_testset branch 2 times, most recently from 1799cdc to e53a90f Compare September 4, 2026 02:58
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github-actions Bot commented Sep 4, 2026

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MemBrowse Memory Report

qemu-armv8a

  • Code: .text +64 B, .text._assert -40 B, .text.clock_initialize -44 B, .text.exec_getsymtab -36 B, .text.fdlist_close -36 B, .text.fdlist_dupfile -88 B, .text.fdlist_extend -56 B, .text.fdlist_get_by_index -44 B, .text.fdlist_install.isra.0 -44 B, .text.file_mq_timedsend_internal -92 B, .text.gethostname -44 B, .text.group_alloc_child -48 B, .text.group_exit_child -36 B, .text.group_find_child -36 B, .text.group_free_child -36 B, .text.group_join -36 B, .text.group_leave -36 B, .text.group_remove_child -36 B, .text.group_remove_children -44 B, .text.irq_attach -44 B, .text.mcount_internal -36 B, .text.moncontrol -72 B, .text.monstartup -40 B, .text.nxclock_gettime -36 B, .text.nxmq_free_msg -68 B, .text.nxsig_action -232 B, .text.nxsig_find_action -40 B, .text.nxsig_pendingset -44 B, .text.nxsig_release -140 B, .text.nxsig_release_action -36 B, .text.nxsig_remove_pendingsignal -20 B, .text.nxsig_tcbdispatch -80 B, .text.pl011_txint -40 B, .text.profil -36 B, .text.profil_timer_handler -36 B, .text.spinlock_t_test_thread -36 B, .text.timer_create -92 B, .text.timer_deleteall -36 B, .text.timer_gethandle -36 B, .text.timer_release -48 B, .text.up_putc -44 B, .text.work_qcancel -52 B, .text.work_qqueue -48 B, .text.work_queue_create -4 B, .text.work_queue_free -40 B, .text.work_thread -96 B, .text.work_thread_create -40 B (-0.7%, 336,116 B)
  • Data: .bss.g_assert_lock -4 B, .bss.g_basetime_lock -4 B, .bss.g_child_pool_lock -4 B, .bss.g_exec_lock -4 B, .bss.g_hostname_lock -4 B, .bss.g_irqlock -4 B, .bss.g_kthread_group -8 B, .bss.g_locktimers -4 B, .bss.g_msgfreelock -4 B, .bss.g_sigaction_spin -4 B, .data.g_uart1priv -8 B (-0.1%, 77,474 B)
    No memory changes detected for:
  • arduino-mega2560
  • esp32-devkitc
  • hifive1-revb
  • mirtoo
  • qemu-intel64
  • rx65n-rsk2mb
  • s698pm-dkit
  • stm32-nucleo-f103rb

@zhangyu-duck
zhangyu-duck force-pushed the arch-atomic-remove-up_testset branch from e53a90f to 3b298ff Compare September 4, 2026 06:06
xiaoxiang781216
xiaoxiang781216 previously approved these changes Sep 4, 2026
acassis
acassis previously approved these changes Sep 4, 2026
@zhangyu-duck
zhangyu-duck dismissed stale reviews from acassis and xiaoxiang781216 via 1395594 September 7, 2026 08:21
@zhangyu-duck
zhangyu-duck force-pushed the arch-atomic-remove-up_testset branch from 3b298ff to 1395594 Compare September 7, 2026 08:21
acassis
acassis previously approved these changes Sep 7, 2026
xiaoxiang781216
xiaoxiang781216 previously approved these changes Sep 7, 2026
Remove the per-arch testset implementation from the spinlock layer.

The testset abstraction predates the unified spinlock.h API and is no
longer used now that all arches provide spin_lock_irqsave()/
spin_unlock_irqrestore() directly.  Drop the per-arch *_testset.{c,S}
implementations and spinlock.h files for arm, sim, sparc, tricore,
x86_64, and xtensa, along with the CXD56_TESTSET,
CXD56_TESTSET_WITH_HWSEM, and CXD56_ATOMIC_WITH_HWSEM Kconfig options
in arch/arm/src/cxd56xx, and simplify the CXD56 semaphore pool loop
in cxd56_sph.c to a single unconditional range.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyu-duck
zhangyu-duck force-pushed the arch-atomic-remove-up_testset branch from a932be1 to 8c5f453 Compare September 7, 2026 15:46
@xiaoxiang781216
xiaoxiang781216 merged commit 9b9d87b into apache:master Sep 8, 2026
54 checks passed
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Labels

Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: ceva Issues related to CEVA architecture Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: tricore Issues related to the TriCore architecture from Infineon Arch: x86_64 Issues related to the x86_64 architecture Arch: xtensa Issues related to the Xtensa architecture Area: Documentation Improvements or additions to documentation Size: M The size of the change in this PR is medium

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