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riscv: Fix CSRRW no-read semantics #30

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riscv: Fix CSRRW no-read semantics #30

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1 change: 1 addition & 0 deletions arch/riscv/helper.h
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Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,7 @@ DEF_HELPER_2(fclass_h, tl, env, i64)

/* Special functions */
DEF_HELPER_3(csrrw, tl, env, tl, tl)
DEF_HELPER_3(csrrw_no_read, void, env, tl, tl)
DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
DEF_HELPER_4(csrrc, tl, env, tl, tl, tl)
DEF_HELPER_2(sret, tl, env, tl)
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6 changes: 6 additions & 0 deletions arch/riscv/op_helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1079,6 +1079,12 @@ void validate_csr(CPUState *env, uint64_t which, uint64_t write)
}
}

void helper_csrrw_no_read(CPUState *env, target_ulong src, target_ulong csr)
{
validate_csr(env, csr, 1);
csr_write_helper(env, src, csr);
}

target_ulong helper_csrrw(CPUState *env, target_ulong src, target_ulong csr)
{
validate_csr(env, csr, 1);
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16 changes: 12 additions & 4 deletions arch/riscv/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3585,8 +3585,12 @@ static void gen_system(DisasContext *dc, uint32_t opc, int rd, int rs1, int rs2,

switch(opc) {
case OPC_RISC_CSRRW:
gen_helper_csrrw(dest, cpu_env, source1, csr_store);
gen_set_gpr(rd, dest);
if(rd == 0) {
gen_helper_csrrw_no_read(cpu_env, source1, csr_store);
} else {
gen_helper_csrrw(dest, cpu_env, source1, csr_store);
gen_set_gpr(rd, dest);
}
break;
case OPC_RISC_CSRRS:
gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
Expand All @@ -3597,8 +3601,12 @@ static void gen_system(DisasContext *dc, uint32_t opc, int rd, int rs1, int rs2,
gen_set_gpr(rd, dest);
break;
case OPC_RISC_CSRRWI:
gen_helper_csrrw(dest, cpu_env, imm_rs1, csr_store);
gen_set_gpr(rd, dest);
if(rd == 0) {
gen_helper_csrrw_no_read(cpu_env, imm_rs1, csr_store);
} else {
gen_helper_csrrw(dest, cpu_env, imm_rs1, csr_store);
gen_set_gpr(rd, dest);
}
break;
case OPC_RISC_CSRRSI:
gen_helper_csrrs(dest, cpu_env, imm_rs1, csr_store, rs1_pass);
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