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riscv: Fix counter access control#28

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whensun:renode-counter-controls
Open

riscv: Fix counter access control#28
whensun wants to merge 1 commit into
antmicro:masterfrom
whensun:renode-counter-controls

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@whensun

@whensun whensun commented Jun 19, 2026

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This PR fixes RISC-V counter access and inhibition behavior in tlib.

It requires U-mode counter access to be allowed by both mcounteren and scounteren, and fixes mcountinhibit handling so inhibited counters stop advancing immediately.

Related to renode/renode#907
Related to renode/renode#910

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