Tutorial chapter_2_first_pyedb_project

Chapter 2 First PyEDB Project

In this chapter, we are going to:

• Explore an EDB
• Setup EDB for simulation
• Import EDB into HFSS 3D Layout

2.1 Preparing an Example EDB

To run PyEDB, you need an .aedb folder. Source of EDB files:

✅ Altium

Altium has an add-in called EDB exportor, which exports EDB nativaly.

edb = Edb("example.aedb")

👉Important:

• .aedb is a folder, not a single file
• Do not rename internal files

✅Cadence

PyEDB converts .brd into EDB directly.

edb = Edb("example.brd")

✅ ODB++ PyEDB converts ODB++ into EDB directly.

edb = Edb("example.tgz")

In this tutorial, we are going to use a demo board in D drive.

from ansys.aedt.core.examples.downloads import download_file

file_edb = download_file(source="pyaedt/edb/ANSYS-HSD_V1.aedb", local_path="D:")

You will find the downloaded EDB in

D:\pyaedt\edb\ANSYS-HSD_V1.aedb

2.2 Explore EDB

from pyedb import Edb

# Open EDB
edb = Edb("D:/pyaedt/edb/ANSYS-HSD_V1.aedb", version="2025.2")

# Save it as a copy
edb.save_as("D:/pyaedt/edb/copy.aedb")

# Count nets
print("Total Nets:", len(edb.nets.nets))

# Count all primitives
print("Total Primitives:", len(edb.layout.primitives))

# Count all stackup layers
print("Total Layer Counts:", len(edb.stackup.signal_layers))

You should see

Total Nets: 348
Total Primitives: 2107
Total Layer Counts: 8

2.3 Setup EDB for Simulation

We are going to define all information in a dictionary.

cfg = {
    "ports": [
        # IC-side coaxial ports on the PCIe Gen4 TX differential pair.
        {
            "name": "port_U1_p",
            "reference_designator": "U1",
            "type": "coax",
            "positive_terminal": {"net": "PCIe_Gen4_TX2_CAP_P"},
        },
        {
            "name": "port_U1_n",
            "reference_designator": "U1",
            "type": "coax",
            "positive_terminal": {"net": "PCIe_Gen4_TX2_CAP_N"},
        },
        # Connector-side circuit ports on the mating edge connector (X1).
        {
            "name": "port_X1_p",
            "reference_designator": "X1",
            "type": "circuit",
            "positive_terminal": {"pin": "B8"},
            "negative_terminal": {"pin": "B7"},
        },
        {
            "name": "port_X1_n",
            "reference_designator": "X1",
            "type": "circuit",
            "positive_terminal": {"pin": "B9"},
            "negative_terminal": {"pin": "B10"},
        },
    ],
    "setups": [
        # SIwave setup
        {
            "name": "siwave_ac",
            "type": "siwave_ac",
            "si_slider_position": 1,
            "freq_sweep": [
                {
                    "name": "Sweep1",
                    "type": "interpolation",
                    "frequencies": [
                        {
                            "distribution": "linear_scale",
                            "start": "50MHz",
                            "stop": "20GHz",
                            "increment": "50MHz",
                        }
                    ],
                }
            ],
        }
    ],
    "operations": {
        "cutout": {
            "signal_list": [
                "PCIe_Gen4_TX2_CAP_P",
                "PCIe_Gen4_TX2_CAP_N",
                "PCIe_Gen4_TX2_P",
                "PCIe_Gen4_TX2_N",
            ],
            "reference_list": ["GND"],
            "custom_extent": [
                [0.014, 0.055],
                [0.03674271504652968, 0.05493094625752912],
                [0.07, 0.039],
                [0.07, 0.034],
                [0.05609890516829415, 0.03395233061637539],
                [0.014, 0.044],
            ],
        }
    }
}

Load configuration

edb.configuration.load(cfg)
edb.configuration.run()

Check the created ports

for i in edb.ports.keys():
    print(i)

You should see

port_U1_p
port_U1_n
port_X1_p
port_X1_n

Save and Close

edb.save()
edb.close()

EDB is prepared for analysis.

2.3 Import EDB into HFSS 3D Layout

EDB is the database contains layout and simulation setups. We need to import it into Ansys Electronics Desktop (AEDT) to create a HFSS 3D Layout design by PyAEDT.

from ansys.aedt.core import Hfss3dLayout

# Import EDB into HFSS 3D Layout
h3d = Hfss3dLayout("D:/pyaedt/edb/copy.aedb", version="2025.2")

# Analyze
h3d.analyze()

# Relase Ansys Electronics Desktop
h3d.release_desktop(False, False)

You should have AEDT open.