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Fix if/else block issues and other issues - #19

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@a1248924 a1248924 commented Aug 4, 2026

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PR Summary by Qodo

Add mirror_input + spi_10mhz AM261x examples; tighten Flow Control labels and SPI timing

✨ Enhancement 🐞 Bug fix 📝 Documentation ⚙️ Configuration changes 🕐 40+ Minutes

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AI Description

• Add AM261x examples: mirror GPIO input and validate 10MHz PRU-to-PRU SPI.
• Expose/validate Flow Control jump targets via new per-block _start/_end labels.
• Convert SPI setup timing to nanoseconds with PRU-clock-based cycle conversion.
Diagram

graph TD
  ui["SysConfig UI"] --> meta["PRU meta JS"] --> asm["Generated asm"] --> ex["AM261x examples"] --> sdk[("MCU+ SDK")]
  meta --> docs["Docs/README"]
  ci["CI workflows"] --> ex
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High-Level Assessment

The following are alternative approaches to this PR:

1. Centralize ns→cycles conversion helper
  • ➕ Eliminates duplicated conversion logic across SPI Read/Write/Transfer blocks
  • ➕ Ensures consistent rounding policy (Math.ceil) and PRU clock lookup
  • ➕ Reduces maintenance risk when timing features evolve
  • ➖ Requires small refactor to introduce/import the shared helper
  • ➖ Slightly harder to cherry-pick into older branches if blocks diverge
2. Stable jump-target IDs (not derived from $name)
  • ➕ Avoids Flow Control target invalidation when users rename blocks
  • ➕ Could make saved configs more resilient over time
  • ➖ Less intuitive than jumping to human-readable block names
  • ➖ Requires migration/UI work; may be overkill if rename churn is low

Recommendation: The chosen approach (generate universal _start/_end labels and build a validated jump-target dropdown from the live design) is the right safety/usability tradeoff for SysConfig-based codegen. A follow-up to DRY ns→cycles conversion into a shared helper would reduce duplication, but changing jump targets to stable IDs is likely not worth the added complexity unless rename breakage becomes common.

Files changed (92) +5232 / -1055 · 2 not counted

Enhancement (14) +1110 / -31
pru_register_allocator.jsEmit per-block _start/_end labels and loop early-exit label +38/-1

Emit per-block _start/_end labels and loop early-exit label

• Introduces universal '<blockName>_start' and (where meaningful) '<blockName>_end' labels as addressable Flow Control targets. Adjusts loop label placement to support jumping back without resetting counters and adds a dedicated loop '_end' early-exit target.

.metadata/sysconfig/.meta/pru_blocks/common/register_allocation/pru_register_allocator.js

flow_control_block.syscfg.jsEnumerate and validate Flow Control jump targets from the design +164/-30

Enumerate and validate Flow Control jump targets from the design

• Builds a live list of valid jump targets (SysConfig end, HALT, and each block’s exposed '_start'/'_end' targets) and validates the selected target. Updates long description/context to match the expanded jump semantics.

.metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js

example.syscfgAdd PRU0 SysConfig design for input mirroring +82/-0

Add PRU0 SysConfig design for input mirroring

• Defines PRU0 block graph to read a GPI bit and set/clear a GPO bit based on an If/Else, looping via Flow Control back to the infinite loop start. Uses the new jump target semantics for reliable loop continuation.

examples/mirror_input/firmware/am261x-lp/icss_m1_pru0_fw/example.syscfg

example.syscfgAdd PRU1 SysConfig design for square-wave generation +85/-0

Add PRU1 SysConfig design for square-wave generation

• Defines PRU1 infinite loop block graph to toggle a GPO bit with delays to generate a repeating waveform. Provides an input stimulus for PRU0 to mirror.

examples/mirror_input/firmware/am261x-lp/icss_m1_pru1_fw/example.syscfg

main.asmAdd PRU firmware entry stub for mirror_input +35/-0

Add PRU firmware entry stub for mirror_input

• Adds a minimal assembly entry that jumps into sysconfig-generated code. Enables CCS/makefile PRU firmware builds with a consistent entry point.

examples/mirror_input/firmware/main.asm

makefileAdd top-level make orchestration for mirror_input example +106/-0

Add top-level make orchestration for mirror_input example

• Adds per-example makefile to build PRU firmware first, then the MCU+ (R5F) host project for AM261x. Includes standard prebuild checks and clean targets.

examples/mirror_input/makefile

main.cAdd FreeRTOS main for mirror_input host application +84/-0

Add FreeRTOS main for mirror_input host application

• Adds standard MCU+ FreeRTOS startup: System/Board init, create main task, run example entrypoint. Provides the host executable entry for the example.

examples/mirror_input/mcuplus/am261x-lp/r5fss0-0_freertos/main.c

empty_example.cHost-side firmware loader for mirror_input (PRU0/PRU1) +101/-0

Host-side firmware loader for mirror_input (PRU0/PRU1)

• Implements PRUICSS open/init and loads PRU0 and PRU1 firmware images into PRU IRAM. Keeps the host running to allow the PRUs to execute continuously.

examples/mirror_input/mcuplus/empty_example.c

example.syscfgAdd PRU0 SysConfig design for 10MHz SPI controller (Transfer) +50/-0

Add PRU0 SysConfig design for 10MHz SPI controller (Transfer)

• Defines PRU0 controller sequence: load constant → SPI Transfer block (MODE1) with ns-based setup/hold timing → Flow Control terminate. Configured to target 10MHz-class operation for validation.

examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/example.syscfg

example.syscfgAdd PRU1 SysConfig design for SPI peripheral response (Write) +49/-0

Add PRU1 SysConfig design for SPI peripheral response (Write)

• Defines PRU1 peripheral sequence: load constant → SPI Write block in peripheral mode → Flow Control terminate. Serves as deterministic responder for PRU0 RX-path validation.

examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/example.syscfg

main.asmAdd PRU firmware entry stub for spi_10mhz +40/-0

Add PRU firmware entry stub for spi_10mhz

• Adds a minimal assembly entry that jumps into sysconfig-generated code plus a halt label for tooling/debug. Enables CCS/makefile PRU builds with a consistent entry point.

examples/spi_10mhz/firmware/main.asm

makefileAdd top-level make orchestration for spi_10mhz example +106/-0

Add top-level make orchestration for spi_10mhz example

• Adds per-example makefile to build PRU firmware first, then the MCU+ (R5F) host project for AM261x. Includes standard prebuild checks and clean targets.

examples/spi_10mhz/makefile

main.cAdd FreeRTOS main for spi_10mhz host application +84/-0

Add FreeRTOS main for spi_10mhz host application

• Adds standard MCU+ FreeRTOS startup: System/Board init, create main task, run example entrypoint. Provides the host executable entry for the example.

examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/main.c

empty_example.cHost-side firmware loader and logs for spi_10mhz validation +86/-0

Host-side firmware loader and logs for spi_10mhz validation

• Loads PRU1 (slave) then PRU0 (controller) firmware via PRUICSS and logs expected observation points (e.g., data in PRU0 R0). Keeps host alive for runtime inspection.

examples/spi_10mhz/mcuplus/empty_example.c

Bug fix (5) +437 / -197
pru_blocks_static_module.syscfg.jsFix UART block detection for simulation warnings +2/-4

Fix UART block detection for simulation warnings

• Switches UART presence detection to use the uart_config module rather than uart_tx/uart_rx modules. Improves correctness of simulation support warnings when UART blocks are used.

.metadata/sysconfig/.meta/pru_blocks/common/pru_blocks_static_module.syscfg.js

conditional_block.syscfg.jsValidate that connected If/Else branches terminate in Flow Control +140/-8

Validate that connected If/Else branches terminate in Flow Control

• Adds a reachability-based validator ensuring every connected T/F branch reaches a Flow Control block (walking both control-flow and data-flow fanout). Prevents branch fall-through into the opposite branch in generated assembly.

.metadata/sysconfig/.meta/pru_blocks/program_control/conditional_block.syscfg.js

pru_spi_read.syscfg.jsSPI Read: treat Data Setup Time as ns and convert to PRU cycles +119/-79

SPI Read: treat Data Setup Time as ns and convert to PRU cycles

• Changes Data Setup Time semantics to nanoseconds and converts to PRU cycles using the configured PRU clock (Math.ceil). Updates min SCLK validation and reorders delay loops to honor setup timing; refreshes frequency guidance to include practical limits.

.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_read.syscfg.js

pru_spi_transfer.syscfg.jsSPI Transfer: ns-based setup timing, updated validation and documentation +82/-45

SPI Transfer: ns-based setup timing, updated validation and documentation

• Converts Data Setup Time to nanoseconds (internally to cycles) and updates per-mode min SCLK validation based on PRU clock. Adjusts macro argument generation to pass setup/hold/setup cycle counts and revises max-frequency guidance (theoretical vs practical PRU-to-PRU loopback).

.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_transfer.syscfg.js

pru_spi_write.syscfg.jsSPI Write: ns-based Data Setup Time and revised max-frequency guidance +94/-61

SPI Write: ns-based Data Setup Time and revised max-frequency guidance

• Converts Data Setup Time to nanoseconds and derives cycle counts from the configured PRU clock for validation and macro parameters. Updates documentation to distinguish theoretical vs practical frequency limits and expands parameter range to ns units.

.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_write.syscfg.js

Refactor (4) +9 / -5
uart_rx_op.syscfg.jsImprove UART RX output port display names for 32/64-bit +2/-1

Improve UART RX output port display names for 32/64-bit

• Updates port metadata to show clearer display names depending on whether the RX frame yields 32-bit or 64-bit output. UI/UX-only change.

.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_rx_op.syscfg.js

uart_tx_op.syscfg.jsImprove UART TX input port display names for 32/64-bit +2/-1

Improve UART TX input port display names for 32/64-bit

• Updates port metadata to show clearer display names depending on whether the TX payload is 32-bit or 64-bit. UI/UX-only change.

.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js

data_splitter.syscfg.jsRename 64-bit input port display name to in64 +1/-1

Rename 64-bit input port display name to in64

• Sets the Data Splitter 64-bit input port displayName to in64 for consistency with other blocks. No functional changes.

.metadata/sysconfig/.meta/pru_blocks/utils/data_splitter.syscfg.js

memory_access_block.syscfg.jsNormalize Memory Access port labels for 32/64-bit read/write +4/-2

Normalize Memory Access port labels for 32/64-bit read/write

• Updates input/output port displayName to reflect width (in64/out64 vs input1/output1) based on data size and mode. UI/UX-only change.

.metadata/sysconfig/.meta/pru_blocks/utils/memory_access_block.syscfg.js

Documentation (11) +330 / -33
README.mdUpdate SPI max-frequency table and document new Flow Control labels +8/-3

Update SPI max-frequency table and document new Flow Control labels

• Adjusts documented maximum SPI frequencies to reflect practical validated limits after timing changes. Documents newly exposed '<blockName>_start/_end' and loop early-exit labels as Flow Control jump targets.

README.md

pru_spi_read_block.mdDocument theoretical vs practical SPI Read limits +8/-6

Document theoretical vs practical SPI Read limits

• Updates SCLK width/frequency table to include theoretical vs practical maxima and explains delay-compensation assumptions. Aligns docs with ns-based setup timing and updated validation model.

docs/input-output/serial-protocol-emulation/pru_spi_read_block.md

pru_spi_transfer_block.mdDocument theoretical vs practical SPI Transfer limits +8/-6

Document theoretical vs practical SPI Transfer limits

• Updates SCLK width/frequency table to include theoretical vs practical maxima and clarifies PRU-to-PRU loopback constraints. Keeps documentation consistent with updated SPI Transfer behavior.

docs/input-output/serial-protocol-emulation/pru_spi_transfer_block.md

pru_spi_write_block.mdDocument theoretical vs practical SPI Write limits +8/-6

Document theoretical vs practical SPI Write limits

• Updates SCLK width/frequency table to include theoretical vs practical maxima and explains the chosen practical delay compensation. Aligns docs with ns-based setup timing changes.

docs/input-output/serial-protocol-emulation/pru_spi_write_block.md

conditional_block.mdClarify If/Else branch termination requirement +15/-4

Clarify If/Else branch termination requirement

• Updates generated assembly example labels and adds explicit guidance that connected branches must terminate via a Flow Control block. Includes guidance for loop-nested If/Else (continue via loop _start, break via loop _end).

docs/program-control/conditional_block.md

flow_control_block.mdDocument jumping to any block’s _start/_end (incl. loop break/continue) +38/-8

Document jumping to any block’s _start/_end (incl. loop break/continue)

• Expands Flow Control documentation from JMP/HALT-only to jumping to any block’s '_start'/'_end' target. Adds examples for continuing/breaking loops and notes live validation of targets.

docs/program-control/flow_control_block.md

loop_block.mdReference Flow Control integration for loop targets +1/-0

Reference Flow Control integration for loop targets

• Adds a note that Flow Control can jump to loop-generated labels/targets. Aligns loop docs with the new jump target model.

docs/program-control/loop_block.md

mirror_input.PNGAdd mirror_input waveform image asset not counted

Add mirror_input waveform image asset

• Adds the waveform screenshot used by the mirror_input README to show input vs mirrored output behavior. Binary asset only.

examples/mirror_input/images/mirror_input.PNG

readme.mdAdd mirror_input example documentation +75/-0

Add mirror_input example documentation

• Documents the two-PRU design (PRU1 generates a signal; PRU0 mirrors input to output) and explains the Loop + If/Else + Flow Control jump pattern. Includes build/run instructions (note: heading text appears to be reused from SPI docs).

examples/mirror_input/readme.md

spi_10mhz.pngAdd spi_10mhz waveform image asset not counted

Add spi_10mhz waveform image asset

• Adds the waveform screenshot used by the spi_10mhz README to illustrate clock/data timing. Binary asset only.

examples/spi_10mhz/images/spi_10mhz.png

readme.mdAdd spi_10mhz example documentation and timing rationale +169/-0

Add spi_10mhz example documentation and timing rationale

• Documents the PRU0 controller (SPI Transfer) and PRU1 peripheral (SPI Write) design used to validate ~10MHz, including timing math and why SPI Write is used on the slave side. Provides pin connections and build/run steps.

examples/spi_10mhz/readme.md

Other (58) +3346 / -789
ccs_build.ymlUpdate AM261x MCU+ SDK version used in CCS CI +3/-3

Update AM261x MCU+ SDK version used in CCS CI

• Bumps the AM261x SDK package/installer URL to a newer release for CI builds. Keeps CCS-based CI aligned with the SDK/tooling required by updated examples/build flow.

.github/workflows/ccs_build.yml

makefile.ymlUpdate AM261x MCU+ SDK version used in makefile CI +3/-3

Update AM261x MCU+ SDK version used in makefile CI

• Bumps the AM261x SDK package/installer URL to a newer release for CI builds. Ensures makefile CI uses the same SDK level expected by the repo.

.github/workflows/makefile.yml

product.jsonAdd AM261x device variants and PRU contexts +29/-1

Add AM261x device variants and PRU contexts

• Adds AM261x variants (e.g., ZNC, ZFG_400) and corresponding ICSS PRU contexts to the product metadata. Enables SysConfig context selection for additional AM261x packages/variants.

.metadata/product.json

example.projectspecUpdate conditional example CCS project linker libraries +5/-5

Update conditional example CCS project linker libraries

• Updates library names to match newer MCU+ SDK naming (FreeRTOS-suffixed drivers/board libs). Prevents CCS link failures on AM261x.

examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec

makefileUpdate conditional example make build for mcelf boot flow +51/-69

Update conditional example make build for mcelf boot flow

• Migrates boot-image targets/cleanup and related constants toward multicore-elf (mcelf) outputs and aligns library naming with the updated SDK layout.

examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile

makefile.defsAdd mcelf artifact patterns to conditional example scrub rules +14/-0

Add mcelf artifact patterns to conditional example scrub rules

• Adds generated-file patterns (including mcelf outputs) for scrub/cleanup. Keeps make builds clean with the updated boot image toolchain.

examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs

makefile_ccs_bootimage_genUpdate CCS post-build boot image generation for conditional example +38/-56

Update CCS post-build boot image generation for conditional example

• Updates CCS post-build boot image generation to use multicore-elf tooling and updated signing scripts/paths. Also adjusts AM261x boot constants (core IDs/run address) to match the new flow.

examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen

example.projectspecUpdate empty example CCS project linker libraries +4/-4

Update empty example CCS project linker libraries

• Updates library names to match newer MCU+ SDK naming (FreeRTOS-suffixed drivers/board libs). Prevents CCS link failures on AM261x.

examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec

makefileUpdate empty example make build for mcelf boot flow +51/-71

Update empty example make build for mcelf boot flow

• Migrates boot-image targets/cleanup and related constants toward multicore-elf (mcelf) outputs and aligns library naming with the updated SDK layout.

examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile

makefile.defsAdd mcelf artifact patterns to empty example scrub rules +14/-0

Add mcelf artifact patterns to empty example scrub rules

• Adds generated-file patterns (including mcelf outputs) for scrub/cleanup. Keeps make builds clean with the updated boot image toolchain.

examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs

makefile_ccs_bootimage_genUpdate CCS post-build boot image generation for empty example +38/-57

Update CCS post-build boot image generation for empty example

• Updates CCS post-build boot image generation to use multicore-elf tooling and updated signing scripts/paths. Also adjusts AM261x boot constants (core IDs/run address) to match the new flow.

examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen

example.projectspecUpdate gray_encoder_4_bit CCS project linker libraries +5/-5

Update gray_encoder_4_bit CCS project linker libraries

• Updates library names to match newer MCU+ SDK naming (FreeRTOS-suffixed drivers/board libs). Prevents CCS link failures on AM261x.

examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec

makefileUpdate gray_encoder_4_bit make build for mcelf boot flow +51/-69

Update gray_encoder_4_bit make build for mcelf boot flow

• Migrates boot-image targets/cleanup and related constants toward multicore-elf outputs and aligns library naming with the updated SDK layout.

examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile

makefile.defsAdd mcelf artifact patterns to gray_encoder_4_bit scrub rules +14/-0

Add mcelf artifact patterns to gray_encoder_4_bit scrub rules

• Adds generated-file patterns (including mcelf outputs) for scrub/cleanup. Keeps make builds clean with the updated boot image toolchain.

examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs

makefile_ccs_bootimage_genUpdate CCS post-build boot image generation for gray_encoder_4_bit +38/-56

Update CCS post-build boot image generation for gray_encoder_4_bit

• Updates CCS post-build boot image generation to use multicore-elf tooling and updated signing scripts/paths. Also adjusts AM261x boot constants (core IDs/run address) to match the new flow.

examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen

example.projectspecUpdate incremental_spi CCS project linker libraries +5/-5

Update incremental_spi CCS project linker libraries

• Updates library names to match newer MCU+ SDK naming (FreeRTOS-suffixed drivers/board libs). Prevents CCS link failures on AM261x.

examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec

makefileUpdate incremental_spi make build for mcelf boot flow +51/-69

Update incremental_spi make build for mcelf boot flow

• Migrates boot-image targets/cleanup and related constants toward multicore-elf outputs and aligns library naming with the updated SDK layout.

examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile

makefile.defsAdd mcelf artifact patterns to incremental_spi scrub rules +14/-0

Add mcelf artifact patterns to incremental_spi scrub rules

• Adds generated-file patterns (including mcelf outputs) for scrub/cleanup. Keeps make builds clean with the updated boot image toolchain.

examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs

makefile_ccs_bootimage_genUpdate CCS post-build boot image generation for incremental_spi +38/-56

Update CCS post-build boot image generation for incremental_spi

• Updates CCS post-build boot image generation to use multicore-elf tooling and updated signing scripts/paths. Also adjusts AM261x boot constants (core IDs/run address) to match the new flow.

examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen

makefileBuild new examples from top-level examples makefile +2/-0

Build new examples from top-level examples makefile

• Adds spi_10mhz and mirror_input to the examples SUBDIRS list. Enables top-level example builds to include the new projects where applicable.

examples/makefile

example.projectspecAdd CCS projectspec for mirror_input PRU0 firmware +83/-0

Add CCS projectspec for mirror_input PRU0 firmware

• Adds CCS project metadata for building PRU0 firmware with TI PRU-CGT. Supports importing/building the PRU0 firmware project in CCS.

examples/mirror_input/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/example.projectspec

linker.cmdAdd linker command file for mirror_input PRU0 firmware +54/-0

Add linker command file for mirror_input PRU0 firmware

• Adds PRU linker configuration for memory/section placement required to build the PRU0 firmware output.

examples/mirror_input/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/linker.cmd

makefileAdd TI PRU-CGT makefile for mirror_input PRU0 firmware +55/-0

Add TI PRU-CGT makefile for mirror_input PRU0 firmware

• Adds make-based PRU0 firmware build producing .out/.h artifacts consumed by the host project. Matches repo build conventions for PRU firmware.

examples/mirror_input/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile

makefile_projectspecAdd makefile-to-CCS integration helper for PRU0 firmware +16/-0

Add makefile-to-CCS integration helper for PRU0 firmware

• Adds supporting file(s) to integrate makefile builds with CCS project workflows for PRU0 firmware.

examples/mirror_input/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile_projectspec

example.projectspecAdd CCS projectspec for mirror_input PRU1 firmware +83/-0

Add CCS projectspec for mirror_input PRU1 firmware

• Adds CCS project metadata for building PRU1 firmware with TI PRU-CGT. Supports importing/building PRU1 firmware project in CCS.

examples/mirror_input/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/example.projectspec

linker.cmdAdd linker command file for mirror_input PRU1 firmware +54/-0

Add linker command file for mirror_input PRU1 firmware

• Adds PRU linker configuration for memory/section placement required to build the PRU1 firmware output.

examples/mirror_input/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/linker.cmd

makefileAdd TI PRU-CGT makefile for mirror_input PRU1 firmware +55/-0

Add TI PRU-CGT makefile for mirror_input PRU1 firmware

• Adds make-based PRU1 firmware build producing .out/.h artifacts consumed by the host project. Matches repo build conventions for PRU firmware.

examples/mirror_input/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile

makefile_projectspecAdd makefile-to-CCS integration helper for PRU1 firmware +16/-0

Add makefile-to-CCS integration helper for PRU1 firmware

• Adds supporting file(s) to integrate makefile builds with CCS project workflows for PRU1 firmware.

examples/mirror_input/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile_projectspec

example.syscfgAdd MCU+ SysConfig for mirror_input host project +325/-0

Add MCU+ SysConfig for mirror_input host project

• Adds AM261x-LP host-side SysConfig setup (PRUICSS instance, GPIO pinmux, logging, memory config). Generates the driver/board configuration for the R5F application.

examples/mirror_input/mcuplus/am261x-lp/r5fss0-0_freertos/example.syscfg

example.projectspecAdd CCS projectspec for mirror_input R5F host build +116/-0

Add CCS projectspec for mirror_input R5F host build

• Adds CCS project metadata for building the mirror_input R5F FreeRTOS host app with ti-arm-clang. Ensures PRU firmware headers are included appropriately.

examples/mirror_input/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec

makefileAdd ti-arm-clang make build for mirror_input R5F host app +336/-0

Add ti-arm-clang make build for mirror_input R5F host app

• Adds makefile build for the R5F host project, including updated boot-image generation and cleanup targets consistent with mcelf-based flows.

examples/mirror_input/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile

makefile.defsAdd generated artifact patterns for mirror_input host scrub +14/-0

Add generated artifact patterns for mirror_input host scrub

• Adds generated-file patterns (including mcelf outputs) used by scrub/cleanup targets. Keeps build output tidy across rebuilds.

examples/mirror_input/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs

makefile_ccs_bootimage_genAdd CCS post-build boot image generation for mirror_input host app +95/-0

Add CCS post-build boot image generation for mirror_input host app

• Adds CCS post-build logic for multicore-elf image generation/signing consistent with the updated AM261x boot flow. Enables CCS build parity with make builds.

examples/mirror_input/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen

makefile_projectspecAdd makefile projectspec helper for mirror_input host build +16/-0

Add makefile projectspec helper for mirror_input host build

• Adds helper metadata to integrate the host makefile build into CCS workflows. Standard example scaffolding.

examples/mirror_input/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec

syscfg_c.rov.xsAdd ROV integration file for mirror_input host build +12/-0

Add ROV integration file for mirror_input host build

• Adds the syscfg_c.rov.xs file used by CCS Runtime Object View / SysConfig integration. Standard MCU+ example scaffolding.

examples/mirror_input/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs

example.projectspecAdd CCS projectspec for spi_10mhz PRU0 firmware +83/-0

Add CCS projectspec for spi_10mhz PRU0 firmware

• Adds CCS project metadata for building PRU0 firmware with TI PRU-CGT. Supports importing/building PRU0 SPI controller firmware project in CCS.

examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/example.projectspec

linker.cmdAdd linker command file for spi_10mhz PRU0 firmware +54/-0

Add linker command file for spi_10mhz PRU0 firmware

• Adds PRU linker configuration for memory/section placement required to build the PRU0 firmware output.

examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/linker.cmd

makefileAdd TI PRU-CGT makefile for spi_10mhz PRU0 firmware +55/-0

Add TI PRU-CGT makefile for spi_10mhz PRU0 firmware

• Adds make-based PRU0 firmware build producing .out/.h artifacts consumed by the host project. Matches repo build conventions for PRU firmware.

examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile

makefile_projectspecAdd makefile-to-CCS integration helper for spi_10mhz PRU0 firmware +16/-0

Add makefile-to-CCS integration helper for spi_10mhz PRU0 firmware

• Adds supporting file(s) to integrate makefile builds with CCS project workflows for PRU0 firmware.

examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile_projectspec

example.projectspecAdd CCS projectspec for spi_10mhz PRU1 firmware +83/-0

Add CCS projectspec for spi_10mhz PRU1 firmware

• Adds CCS project metadata for building PRU1 firmware with TI PRU-CGT. Supports importing/building PRU1 SPI peripheral firmware project in CCS.

examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/example.projectspec

linker.cmdAdd linker command file for spi_10mhz PRU1 firmware +54/-0

Add linker command file for spi_10mhz PRU1 firmware

• Adds PRU linker configuration for memory/section placement required to build the PRU1 firmware output.

examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/linker.cmd

makefileAdd TI PRU-CGT makefile for spi_10mhz PRU1 firmware +55/-0

Add TI PRU-CGT makefile for spi_10mhz PRU1 firmware

• Adds make-based PRU1 firmware build producing .out/.h artifacts consumed by the host project. Matches repo build conventions for PRU firmware.

examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile

makefile_projectspecAdd makefile-to-CCS integration helper for spi_10mhz PRU1 firmware +16/-0

Add makefile-to-CCS integration helper for spi_10mhz PRU1 firmware

• Adds supporting file(s) to integrate makefile builds with CCS project workflows for PRU1 firmware.

examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile_projectspec

example.syscfgAdd MCU+ SysConfig for spi_10mhz host project +327/-0

Add MCU+ SysConfig for spi_10mhz host project

• Adds AM261x-LP host-side SysConfig setup (PRUICSS instance, pinmux, logging, memory config). Generates the driver/board configuration for the R5F application.

examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/example.syscfg

example.projectspecAdd CCS projectspec for spi_10mhz R5F host build +116/-0

Add CCS projectspec for spi_10mhz R5F host build

• Adds CCS project metadata for building the spi_10mhz R5F FreeRTOS host app with ti-arm-clang. Ensures PRU firmware headers are included appropriately.

examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec

makefileAdd ti-arm-clang make build for spi_10mhz R5F host app +336/-0

Add ti-arm-clang make build for spi_10mhz R5F host app

• Adds makefile build for the R5F host project, including updated boot-image generation and cleanup targets consistent with mcelf-based flows.

examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile

makefile.defsAdd generated artifact patterns for spi_10mhz host scrub +14/-0

Add generated artifact patterns for spi_10mhz host scrub

• Adds generated-file patterns (including mcelf outputs) used by scrub/cleanup targets. Keeps build output tidy across rebuilds.

examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs

makefile_ccs_bootimage_genAdd CCS post-build boot image generation for spi_10mhz host app +95/-0

Add CCS post-build boot image generation for spi_10mhz host app

• Adds CCS post-build logic for multicore-elf image generation/signing consistent with the updated AM261x boot flow. Enables CCS build parity with make builds.

examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen

makefile_projectspecAdd makefile projectspec helper for spi_10mhz host build +16/-0

Add makefile projectspec helper for spi_10mhz host build

• Adds helper metadata to integrate the host makefile build into CCS workflows. Standard example scaffolding.

examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec

syscfg_c.rov.xsAdd ROV integration file for spi_10mhz host build +12/-0

Add ROV integration file for spi_10mhz host build

• Adds the syscfg_c.rov.xs file used by CCS Runtime Object View / SysConfig integration. Standard MCU+ example scaffolding.

examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs

example.projectspecUpdate spi_loopback CCS project linker libraries +5/-5

Update spi_loopback CCS project linker libraries

• Updates library names to match newer MCU+ SDK naming (FreeRTOS-suffixed drivers/board libs). Prevents CCS link failures on AM261x.

examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec

makefileUpdate spi_loopback make build for mcelf boot flow +51/-69

Update spi_loopback make build for mcelf boot flow

• Migrates boot-image targets/cleanup and related constants toward multicore-elf outputs and aligns library naming with the updated SDK layout.

examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile

makefile.defsAdd mcelf artifact patterns to spi_loopback scrub rules +14/-0

Add mcelf artifact patterns to spi_loopback scrub rules

• Adds generated-file patterns (including mcelf outputs) for scrub/cleanup. Keeps make builds clean with the updated boot image toolchain.

examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs

makefile_ccs_bootimage_genUpdate CCS post-build boot image generation for spi_loopback +38/-56

Update CCS post-build boot image generation for spi_loopback

• Updates CCS post-build boot image generation to use multicore-elf tooling and updated signing scripts/paths. Also adjusts AM261x boot constants (core IDs/run address) to match the new flow.

examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen

example.projectspecUpdate uart_crc CCS project linker libraries +5/-5

Update uart_crc CCS project linker libraries

• Updates library names to match newer MCU+ SDK naming (FreeRTOS-suffixed drivers/board libs). Prevents CCS link failures on AM261x.

examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec

makefileUpdate uart_crc make build for mcelf boot flow +51/-69

Update uart_crc make build for mcelf boot flow

• Migrates boot-image targets/cleanup and related constants toward multicore-elf outputs and aligns library naming with the updated SDK layout.

examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile

makefile.defsAdd mcelf artifact patterns to uart_crc scrub rules +14/-0

Add mcelf artifact patterns to uart_crc scrub rules

• Adds generated-file patterns (including mcelf outputs) for scrub/cleanup. Keeps make builds clean with the updated boot image toolchain.

examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs

makefile_ccs_bootimage_genUpdate CCS post-build boot image generation for uart_crc +38/-56

Update CCS post-build boot image generation for uart_crc

• Updates CCS post-build boot image generation to use multicore-elf tooling and updated signing scripts/paths. Also adjusts AM261x boot constants (core IDs/run address) to match the new flow.

examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen

@qodo-code-review

qodo-code-review Bot commented Aug 4, 2026 •

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Code Review by Qodo


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1. Choosing Halt emits a JMP with no target 🐞 ⭐
Description
With the new jumpTarget dropdown set to "HALT", constant1 returns an empty string. The
instruction is still built from the hidden opCode, which has no getValue and keeps its default
"JMP", so the allocator generates JMP  with no operand instead of HALT. Every design that picks
Halt in the new dropdown then produces assembly the assembler rejects. In the simulator it becomes
an unresolved jump rather than a stop.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
When Flow Control `jumpTarget` is "HALT", the hidden `opCode` stays "JMP" and `constant1` is "", so the generated instruction is `JMP ` with no operand.

## Fix Focus Areas
- .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js[212-252]

## Recommended Fix
Give `opCode` a `getValue: (inst) => inst.jumpTarget === "HALT" ? "HALT" : "JMP"`, or emit the opcode from `jumpTarget` some other way. If legacy files that set `opCode = "HALT"` still need to work, map that value to HALT as well.

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2. An unterminated branch passes validation 🐞 ⭐
Description
branchTerminates combines the executable next path and data-only output1 consumers with an OR,
so one consumer reaching Flow Control masks a dead end on next. If a branch block sends data to
Flow Control but its next chain ends without a terminator, validation accepts the branch although
execution can fall through.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
A data consumer can conceal an unterminated executable conditional branch.
## Fix Focus Areas
- .metadata/sysconfig/.meta/pru_blocks/program_control/conditional_block.syscfg.js[19-71]
## Recommended Fix
Determine termination from executable control-flow successors, requiring each executable path to terminate; do not let an output1 data consumer override a failing next path.

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3. Jumps to blocks named with 'loop' go astray 🐞 ⭐
Description
constant1 rewrites any jump target whose text contains "Loop_" or "loop_" plus "start" as if it
were a finite loop. Names matching Loop_(\d+) become endloop_N; any other name has _start
removed and becomes a bare label that the code never emits. A user block named, say, Loop_1_delay
or main_loop_gpo (both default-style names) therefore jumps to some loop's end, or to an undefined
symbol that breaks assembly, instead of to the selected block's entry.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
The Flow Control `constant1` getValue remaps any target containing "Loop_"/"loop_" and "start", so ordinary blocks with such names get jumps to the wrong label or to an undefined one.

## Fix Focus Areas
- .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js[238-250]
- .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js[42-57]

## Recommended Fix
Only remap a target when it exactly equals `${loopInst.$name}_start` for a finite loop instance. Find that instance in `system.modules["/pru_blocks/program_control/loop_block"].$instances` and map to `endloop_${index}`. Pass every other target through unchanged. Also build the finite-loop dropdown entry from `inst.$name` rather than `Loop_${i}`, so renamed loops still appear.

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4. Renamed loops lose their break target 🐞 ⭐
Description
getValidJumpTargets constructs a finite-loop option named Loop_${i}_start, but the allocator
emits ${instanceName}_start and the option is filtered against emitted labels. When a finite loop
has a custom instance name, its break target disappears from the dropdown and a saved selection
fails validation.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
Finite loops with custom names cannot expose their Flow Control break target.
## Fix Focus Areas
- .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js[40-85]
- .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js[238-249]
## Recommended Fix
Construct finite-loop choices from their actual emitted instance-name labels, and translate a selected finite-loop target to its corresponding endloop label without relying on a `Loop_N` name.

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View medium (7)
Remediation recommended
5. AI instructions point to a missing file 🐞 ⭐
Description
additionalInstructions tells the AI workflow to read Agents.md, while the committed filename is
AGENTS.md. On a case-sensitive filesystem, following that prerequisite cannot open the named file
before block configuration.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
The AI prerequisite names a file that does not exist on case-sensitive filesystems.
## Fix Focus Areas
- .metadata/sysconfig/.meta/ai.component.js[5-5]
## Recommended Fix
Change `Agents.md` to the repository's actual filename, `AGENTS.md`.

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6. Group entry points get false warnings 🐞 ⭐
Description
The new unreachable-label check warns on every unvisited _start label, including group entry
points. Groups are emitted for explicit calls from application assembly rather than reached from the
simulator’s default entry point, so a normal simulation warns about valid groups.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
Normal groups produce misleading unreachable-label warnings.
## Fix Focus Areas
- .metadata/sysconfig/.meta/pru_blocks/common/pru_blocks_static_module.syscfg.js[1247-1271]
## Recommended Fix
Identify group entry labels and exclude them from warnings based solely on the default simulation path.

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7. AI docs for two blocks are empty stubs 🐞 ⭐
Description
docs_ai/utils/look_up_table.md and docs_ai/utils/data_splitter.md contain only a placeholder
(function getLongDescription() { ... }), even though both blocks' long descriptions now tell the
AI to read these files first. The getAIContext content for the lookup table, which held the
parameter tables, valid values and examples, was deleted in the same change. The AI assistant
therefore has no configuration reference for these blocks.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
The docs_ai files for look_up_table and data_splitter are placeholders, while the block descriptions send the AI to them.

## Fix Focus Areas
- docs_ai/utils/look_up_table.md[1-5]
- docs_ai/utils/data_splitter.md[1-5]

## Recommended Fix
Write full docs (parameters, valid values, example scripting snippets, connection notes) in the same format as the other docs_ai files. For look_up_table, reuse the removed `getAIContext` content.

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8. AM261x incremental SPI example sends no SPI 🐞 ⭐
Description
The am261x incremental_spi firmware design removed the pru_spi_write block and replaced it with
an If/Else plus two Flow Control blocks. It also raised loopCount to 15, so the loop now only
increments a register and never transmits. The example README and the R5F side still describe
sending 1..10 over SPI, so on AM261x the example no longer demonstrates what it is named for.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
The AM261x incremental_spi firmware no longer contains a SPI Write block, so nothing is transmitted.

## Fix Focus Areas
- examples/incremental_spi/firmware/am261x-lp/icss_m1_pru0_fw/example.syscfg[12-76]

## Recommended Fix
Put `PRU0_SPI_Write_0` back in the loop (with its CS signal setting), fed from `Arithmetic_0.output1`, and end its chain with a Flow Control "continue" as the am243x variant does. Restore `loopCount = 10` to match the README. Or, if the new behaviour is intended, update the README.

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9. Example PRUs run past the end of main 🐞 ⭐
Description
The empty and spi_loopback examples removed opCode = "HALT" while leaving Flow Control to jump to
sysconfig_generated_end, a label at the end of main.asm with no stopping instruction. When that
jump executes, the PRU passes the label and falls through beyond .text:main into the following
.text section, which contains generated code, instead of stopping at the former termination point.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
The empty and spi_loopback firmware examples now jump to an end label that has no stopping instruction, rather than halting as they did before.

## Fix Focus Areas
- examples/spi_loopback/firmware/main.asm[37-37]
- examples/empty/firmware/main.asm[38-38]
- examples/empty/firmware/am243x-evm/icss_g0_pru0_fw/example.syscfg[15-19]
- examples/empty/firmware/main.asm[34-38]

## Recommended Fix
Add a `halt` immediately after `sysconfig_generated_end:` in both examples' `main.asm` files, or set their active Flow Control `jumpTarget = "HALT"` in the syscfg files. Verify the other examples whose HALT assignments were removed.

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10. Valid jump targets depend on stale state 🐞 ⭐
Description
Both getValidJumpTargets (used by the dropdown options and by validate) only accept targets
found in getPruRegisterAllocationSummary().labels. That summary is a module-level variable
populated only by allocatePruRegisters() inside the static module's validate. If the Flow
Control validate or options run before that, or on a first load, the summary is undefined or
reflects the previous design. Valid targets such as Loop_0_start or startloop_0 are then
rejected with an error, and the dropdown omits blocks that were just added.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
Flow Control jump-target validation and options are filtered against the allocator's cached label list, which is only filled during the static module's validate. Depending on evaluation order, valid targets can be rejected or missing.

## Fix Focus Areas
- .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js[13-86]
- .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js[97-100]

## Recommended Fix
Build the target list directly from `system.modules` instances, using the same naming rules the allocator uses, and drop the `emittedLabels` filter. Alternatively, call `allocatePruRegisters()` on demand when the summary is undefined, before filtering.

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11. Non-semantic block $name values 📘 Rule 2
Description
The new PRU0 and PRU1 SysConfig designs use generated, ambiguous type-and-index block instance names
(e.g., Load_Constant_0, If_Else_0, PRU0_GPI_INSTANCE_0, PRU1_GPO_INSTANCE_0, Delay_0,
Loop_0) instead of functional, purpose-oriented names. This violates Compliance ID 1 and makes
reviews, wiring validation, and future edits more error-prone by increasing the chance of selecting
or connecting the wrong block.
Agent prompt
The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
The PRU0 and PRU1 SysConfig designs assign generated, ambiguous type-and-index instance names (e.g., `*_0`, `*_INSTANCE_0`) instead of functional/semantic names that reflect each block’s role, increasing the likelihood of wiring/connection mistakes during review and future edits.

## Issue Context
Compliance ID 1 requires block instance names that clearly describe purpose/value (not generated naming like `Load_Constant_0`, `If_Else_0`, `Delay_0`, `Loop_0`, `PRU0_GPI_INSTANCE_0`, `PRU1_GPO_INSTANCE_0`). This is especially important when multiple similar blocks exist (e.g., multiple GPO/GPI blocks, conditionals, constants, delays/loops), where ambiguous names make it easier to select or connect the wrong block.

## Fix Focus Areas
- examples/mirror_input/firmware/am261x-lp/icss_m1_pru0_fw/example.syscfg[33-55]
- examples/mirror_input/firmware/am261x-lp/icss_m1_pru1_fw/example.syscfg[28-56]

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Comment thread examples/mirror_input/firmware/am261x-lp/icss_m1_pru0_fw/example.syscfg Outdated
Comment thread .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js Outdated
@a1248924
a1248924 force-pushed the a1248924_mirror_input_example branch 2 times, most recently from 461a2a3 to a8bf168 Compare August 4, 2026 11:02
@a1248924
a1248924 force-pushed the a1248924_mirror_input_example branch 3 times, most recently from bb486a3 to a69f359 Compare September 20, 2026 12:26
@a1248924 a1248924 linked an issue Sep 20, 2026 that may be closed by this pull request

@pratheesh pratheesh left a comment

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Thanks for this. The Flow Control jump-target work is a good addition. I generated and tested several designs against this head (a69f359) and found some problems I think should be fixed before merge. They're listed most severe first.

How I checked: SysConfig 1.28.0 CLI against the PR-head .metadata/product.json (AM261x_ZFG, icss_m1_pru0), with the generated asm assembled using clpru 2.3.3. I checked loop behaviour on the TI pru-simulator (cycle-accurate hardware-LOOP model) but have not tested it on silicon.

1. <Loop>_end "break" behaves like continue on finite loops

Loop_0_end: is emitted at the same address as endloop_0. A JMP to the LOOP end address triggers the hardware loop-back. I simulated the exact generated asm with a 5-count loop whose branch jumps to Loop_0_end. It still ran the body 5 times and then halted, where a real break would run it once. Infinite loops are fine, because their _end comes after a QBA and no hardware loop is involved.
Suggested fix: place the break target at an address other than endloop_N (for example one instruction past a trampoline), then confirm on silicon.

2. <Loop>_start re-arms the LOOP, so the documented "continue" pattern never terminates

The label sits between LDI and LOOP. The code comment says a jump there "resumes with the current counter value", but that isn't what happens: re-executing LOOP reloads the count from the register. The conditional_block/flow_control docs tell users to end both branches with JMP Loop_0_start. I simulated that pattern with GPI high and got 714 body entries in 5000 steps with no halt. Also, if the counter register gets reallocated inside the body, the count would be garbage.

3. The dropdown offers targets that are never emitted, and validation accepts them

getValidJumpTargets() lists _start/_end for every /pru_blocks/ instance. But addToPruRegisterAllocationSummary drops 0-cycle entries for blocks with an empty opCode (Memory Variable, LUT). A design with jumpTarget = "Mem_Var_start" passes SysConfig validation, and then clpru fails with E0300 undefined symbol Mem_Var_start. The docs say validation prevents exactly this failure. Unconnected blocks, which pushInstruction never visits, are probably affected the same way.

4. Breaking change: legacy Flow Control designs no longer load

opCode is now a getter-only hidden config. On this head, main's examples/empty/.../example.syscfg (which sets opCode = "HALT") fails with Error: cannot set 'opCode' to 'HALT'. The repo examples were migrated by deleting that line, which also changes HALT into JMP sysconfig_generated_end plus a label in main.asm. User designs have no migration path. Could the old setter be accepted and mapped, or could a migration note be added?

5. SPI Data Setup Time units change silently from cycles to ns

Existing designs will get a much shorter setup time: a value of 10 used to mean 10 cycles and now means 10 ns, which is 2 cycles at 200 MHz. CS Setup/Hold were labelled ns but were previously passed through as raw cycles. This PR fixes that bug, but it also changes behaviour (500 used to mean 2.5 µs and now means 500 ns). This needs a release note or migration.

6. The spi_10mhz example contradicts its README

  • The syscfg has SCLK high=16, low=6, but the README says 14/6.
  • PRU0 (the controller) leaves pruClkFreq at its default of 200 while PRU1 sets 225. That gives SCLK = 9.09 MHz at 200 or 10.23 MHz at 225, never 10 MHz.
  • The caption says "1 bit = 10ns" (should be 100 ns).
  • The README block table now says "SPI Transfer up to 7.69 MHz", which contradicts this 10 MHz SPI Transfer example.

7. If_Else_N_start comes after the input computations

The docs say "jump to an If/Else's _start to re-evaluate it". A jump there compares stale registers that may already have been reallocated, and it does not re-read the inputs.

8. branchTerminates ORs paths (from reading the code; not tested)

It accepts a branch if any next/data-consumer path reaches Flow Control, and it treats data-flow edges as control flow. The docstring says every path must reach it.

9. Small defects

  • uart_tx_op: the input port displayName is "output1" (copy-paste error).
  • spi_write docs still say MODE0 needs a minimum High of 2 for 25 MHz, but validation now allows High=1 (7 cycles, 28.57 MHz).
  • mirror_input readme: the title is "SPI Transfer at 10MHz", it says Loop_0_start where the config uses startloop_0, and it references a pin table that doesn't exist.
  • The mirror R5F syscfg still has leftover SPI pinmux entries (PRU1 GPIO5/6/11, PRU0 GPIO2/7/9).
  • The mirror main.c has dead AM64x/AM243x RTU/TX loads in an AM261x-only example.

10. Scope

The title says "mirror input example", but the PR also includes:

  • the Flow Control/label redesign
  • the SPI timing rework
  • an AM261x CI SDK bump from 10.02.00.15 to 26.00.00.06.STS (mcelf boot images and freertos.* libs, which breaks older SDKs; the README doesn't state the new minimum SDK)
  • new ZNC and ZFG_400 device variants

Splitting these into separate PRs would make review and bisecting much easier. The PR description is also empty.


Note: CI is green, but that only shows the shipped examples compile. None of them uses a finite-loop jump or a declaration-block jump target, which is where items 1 to 3 appear. The qodo bot also flagged #4. Its claim that the repo examples still set opCode is out of date at this head.

Comment thread .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js Outdated
* branches must recursively terminate the same way.
* Returns an error message, or null if the branch terminates correctly.
*/
function branchTerminates(headInst, ownerName, branchLabel) {

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From reading the code: walk accepts the branch if any reachable next/data-consumer path hits Flow Control, and it treats output1 data edges as control flow. The docstring says every path must terminate (item 8).

Comment thread .metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js Outdated
@a1248924 a1248924 changed the title A1248924 mirror input example Fix if/else block issues and other issues Oct 8, 2026
@a1248924
a1248924 force-pushed the a1248924_mirror_input_example branch from 5a3debf to 84bc91f Compare October 9, 2026 07:48
- add docs_ai
signed-off by Ayushman <a-ayushman@ti.com>
- add option to jump to start of block from flow control
- correct/update documentation for conditional, flow control, loop block
- enforce graph of blocks termination with flow control
- add warning for unreachable blocks
- add details on how to implement break/continue for loop

signed-off by Ayushman <a-ayushman@ti.com>
- update r5f code to use latest sdk
- remove spi_10mhz example, to be added as seperate PR

signed-off by Ayushman <a-ayushman@ti.com>
@a1248924
a1248924 force-pushed the a1248924_mirror_input_example branch from 84bc91f to 763a2fa Compare October 9, 2026 08:32
- update readme

signed-off by Ayushman <a-ayushman@ti.com>
@a1248924
a1248924 force-pushed the a1248924_mirror_input_example branch from 763a2fa to 30dbcaa Compare October 9, 2026 08:39
@a1248924

a1248924 commented Oct 9, 2026

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/agentic_review

@pratheesh pratheesh left a comment

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Thanks for the update. Several things are clearly better: the Flow Control target list is now filtered to labels that are actually emitted, so the Memory Variable case is rejected in SysConfig instead of failing in the assembler; the If/Else check that every connected branch ends in a Flow Control is a good addition and works on the shipped conditional example; and the scope is much tighter now that the SPI and mirror/10 MHz example changes are out.

A few things still need attention:

  1. Breaking out of a finite loop. Jumping to the start of the block connected after the loop (as the new docs describe) still behaves like a continue. In the generated assembly that block's _start label sits at the same address as endloop_N, so the hardware loop-back still triggers. I simulated a 5-count loop with an If/Else whose true branch clears an output and jumps to the next block's _start: the clear executed 5 times instead of once, and the next block ran only after the fifth pass. Infinite loops are fine. Could the exit target be placed past the loop end (for example one instruction after, or via a small trampoline), ideally with an example or test that breaks out of a finite loop? Worth confirming on hardware too.
  2. Continue in a finite loop. The docs now correctly say that jumping to <Loop>_start re-arms LOOP, but the option is still offered for finite loops without any warning. In simulation a Flow Control that jumps there never terminates. Consider hiding it for finite loops, or warning when it is selected.
  3. Existing designs. Designs saved with opCode = "HALT" still fail to load (cannot set 'opCode' to 'HALT'). A short migration note, or accepting opCode and mapping it to jumpTarget, would avoid breaking saved projects.
  4. New validation false positives. A finite loop that is the last block (no next) is reported as "Disconnected chunk ... missing Flow Control termination" even when its body ends in Flow Controls. The "Unreachable chunk" warnings are based on a single fixed-input simulation, so correct If/Else designs, including the shipped conditional example, show warnings for the branch the simulated input doesn't take. Static reachability, or softer wording, would avoid noise.
  5. Branch termination check. branchTerminates still accepts a branch if any one next/data-consumer path reaches a Flow Control. Requiring every control-flow path (and not counting data-flow edges) would match the comment and the "run both branches" failure it is meant to prevent.
  6. Minor: README and the error text still mention _end targets in the dropdown although they were removed; If_Else_N_start sits after the input computations, so jumping there re-compares stale registers (worth a sentence in the docs); the description is still empty, and the docs_ai/ and AGENTS.md changes might be easier to review as their own PR.

@a1248924

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regarding this comment :
5. Branch termination check. branchTerminates still accepts a branch if any one next/data-consumer path reaches a Flow Control. Requiring every control-flow path (and not counting data-flow edges) would match the comment and the "run both branches" failure it is meant to prevent.

lets say we have this block combination:
image

i think we dont expect the user to connect every flow control using next/prev and for if/else blocks specifically the inputs are two for the block and it has only one prev port so the user cannot connect both the branches next to the if/else's prev

that is why for if/else block we have a seperate check that both T/F branch should end in a flow control and it behaves as expected, the check for a chunk of blocks to end in flow control is seperate than this

@a1248924

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for the loop block issue not going out and re-entering the loop, i have added a NOP after the loop block
i will check and review once from my side if there is any case in which this is failing or producing incorrect code

… not overlap with endloop

- update documentation
- terminating loop block may not have flow control termimation
- disable jumping to loop_start if using finite loop
- add opCode="HALT" support so that previous designs do not fail
signed-off by  Ayushman <a-ayushman@ti.com>
@a1248924
a1248924 force-pushed the a1248924_mirror_input_example branch from b6ed027 to c4c3445 Compare October 14, 2026 11:27
@pratheesh-ti

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/agentic_review

Comment on lines +59 to +63
handled = walk(nextInst) || handled;
}
for (const consumer of outputConsumers) {
handled = walk(consumer) || handled;
}

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Action required

3. An unterminated branch passes validation 🐞 Bug ≡ Correctness

branchTerminates combines the executable next path and data-only output1 consumers with an OR,
so one consumer reaching Flow Control masks a dead end on next. If a branch block sends data to
Flow Control but its next chain ends without a terminator, validation accepts the branch although
execution can fall through.
Agent Prompt
## Issue description
A data consumer can conceal an unterminated executable conditional branch.
## Fix Focus Areas
- .metadata/sysconfig/.meta/pru_blocks/program_control/conditional_block.syscfg.js[19-71]
## Recommended Fix
Determine termination from executable control-flow successors, requiring each executable path to terminate; do not let an output1 data consumer override a failing next path.

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Comment on lines +1247 to +1252
// Unreachable-chunk warnings: only for block start labels, once globally
for (const lbl of emittedLabels) {
if (!visitedLabels.has(lbl)) {
const isBlockStart = lbl.endsWith('_start') || lbl.startsWith('startloop_');
// Skip endloop labels: unvisited endloop is normal (loop exits after iterations)
if (isBlockStart && !warnedLabelsGlobal.has(lbl)) {

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Remediation recommended

6. Group entry points get false warnings 🐞 Bug ◔ Observability

The new unreachable-label check warns on every unvisited _start label, including group entry
points. Groups are emitted for explicit calls from application assembly rather than reached from the
simulator’s default entry point, so a normal simulation warns about valid groups.
Agent Prompt
## Issue description
Normal groups produce misleading unreachable-label warnings.
## Fix Focus Areas
- .metadata/sysconfig/.meta/pru_blocks/common/pru_blocks_static_module.syscfg.js[1247-1271]
## Recommended Fix
Identify group entry labels and exclude them from warnings based solely on the default simulation path.

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valid, will exclude group blocks

Comment thread .metadata/sysconfig/.meta/ai.component.js
Comment on lines +243 to +248
if ((String(inst["jumpTarget"]).includes('Loop_') || String(inst["jumpTarget"]).includes('loop_')) && String(inst["jumpTarget"]).includes('start')) {
const jt = String(inst["jumpTarget"]);
const match = jt.match(/Loop_(\d+)/);
if (match) return `endloop_${match[1]}`;
return jt.replace(/_start$/, '').replace(/^Loop_/, 'endloop_');
}

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Action required

5. Jumps to blocks named with 'loop' go astray 🐞 Bug ≡ Correctness

constant1 rewrites any jump target whose text contains "Loop_" or "loop_" plus "start" as if it
were a finite loop. Names matching Loop_(\d+) become endloop_N; any other name has _start
removed and becomes a bare label that the code never emits. A user block named, say, Loop_1_delay
or main_loop_gpo (both default-style names) therefore jumps to some loop's end, or to an undefined
symbol that breaks assembly, instead of to the selected block's entry.
Agent Prompt
## Issue description
The Flow Control `constant1` getValue remaps any target containing "Loop_"/"loop_" and "start", so ordinary blocks with such names get jumps to the wrong label or to an undefined one.

## Fix Focus Areas
- .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js[238-250]
- .metadata/sysconfig/.meta/pru_blocks/program_control/flow_control_block.syscfg.js[42-57]

## Recommended Fix
Only remap a target when it exactly equals `${loopInst.$name}_start` for a finite loop instance. Find that instance in `system.modules["/pru_blocks/program_control/loop_block"].$instances` and map to `endloop_${index}`. Pass every other target through unchanged. Also build the finite-loop dropdown entry from `inst.$name` rather than `Loop_${i}`, so renamed loops still appear.

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main:
JMP sysconfig_generated_start
sysconfig_generated_end:

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Remediation recommended

8. Example prus run past the end of main 🐞 Bug ☼ Reliability

The empty and spi_loopback examples removed opCode = "HALT" while leaving Flow Control to jump to
sysconfig_generated_end, a label at the end of main.asm with no stopping instruction. When that
jump executes, the PRU passes the label and falls through beyond .text:main into the following
.text section, which contains generated code, instead of stopping at the former termination point.
Agent Prompt
## Issue description
The empty and spi_loopback firmware examples now jump to an end label that has no stopping instruction, rather than halting as they did before.

## Fix Focus Areas
- examples/spi_loopback/firmware/main.asm[37-37]
- examples/empty/firmware/main.asm[38-38]
- examples/empty/firmware/am243x-evm/icss_g0_pru0_fw/example.syscfg[15-19]
- examples/empty/firmware/main.asm[34-38]

## Recommended Fix
Add a `halt` immediately after `sysconfig_generated_end:` in both examples' `main.asm` files, or set their active Flow Control `jumpTarget = "HALT"` in the syscfg files. Verify the other examples whose HALT assignments were removed.

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* References between modules.
*/
loop_block1.$groupContents = [load_constant_block1, load_constant_block2, arithmetic_block1, pru_spi_write1];
loop_block1.$groupContents = [load_constant_block1, load_constant_block2, arithmetic_block1, conditional_block1, load_constant_block3, flow_control_block1, flow_control_block2];

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Remediation recommended

9. Am261x incremental spi example sends no spi 🐞 Bug ≡ Correctness

The am261x incremental_spi firmware design removed the pru_spi_write block and replaced it with
an If/Else plus two Flow Control blocks. It also raised loopCount to 15, so the loop now only
increments a register and never transmits. The example README and the R5F side still describe
sending 1..10 over SPI, so on AM261x the example no longer demonstrates what it is named for.
Agent Prompt
## Issue description
The AM261x incremental_spi firmware no longer contains a SPI Write block, so nothing is transmitted.

## Fix Focus Areas
- examples/incremental_spi/firmware/am261x-lp/icss_m1_pru0_fw/example.syscfg[12-76]

## Recommended Fix
Put `PRU0_SPI_Write_0` back in the loop (with its CS signal setting), fed from `Arithmetic_0.output1`, and end its chain with a Flow Control "continue" as the am243x variant does. Restore `loopCount = 10` to match the README. Or, if the new behaviour is intended, update the README.

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Comment on lines +1 to +5
```javascript
function getLongDescription() { ... } (see source file for full definition)
```

Source file: utils\look_up_table.syscfg.js No newline at end of file

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Remediation recommended

11. Ai docs for two blocks are empty stubs 🐞 Bug ⚙ Maintainability

docs_ai/utils/look_up_table.md and docs_ai/utils/data_splitter.md contain only a placeholder
(function getLongDescription() { ... }), even though both blocks' long descriptions now tell the
AI to read these files first. The getAIContext content for the lookup table, which held the
parameter tables, valid values and examples, was deleted in the same change. The AI assistant
therefore has no configuration reference for these blocks.
Agent Prompt
## Issue description
The docs_ai files for look_up_table and data_splitter are placeholders, while the block descriptions send the AI to them.

## Fix Focus Areas
- docs_ai/utils/look_up_table.md[1-5]
- docs_ai/utils/data_splitter.md[1-5]

## Recommended Fix
Write full docs (parameters, valid values, example scripting snippets, connection notes) in the same format as the other docs_ai files. For look_up_table, reuse the removed `getAIContext` content.

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both true and false conditions executed for if/else block

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