fix: resolve transitive protected-bus merging in zero-impedance reduction

[mcllerena]

When running the AC Power Flow on EI cases (2026/2027/2030/2035) for SLL and SUM scenarios. The following error triggers for AC-VOLTAGE VSC control

ERROR: Two VSC converters both use AC-voltage control at bus 181730; duplicate |V_ac| pins make the Jacobian singular (or the setpoints infeasible). Use reactive-power control for one of them.
Stacktrace:
[1] error(s::String)
@ Base ./error.jl:44
[2] _validate_vsc_ac_controls(dcn::PowerFlows.DCNetwork, bus_types::SubArray{ACBusTypes, 1, Matrix{…}, Tuple{…}, true})
@ PowerFlows ~/Documents/marck/GDO/PowerFlows.jl/src/vsc_utils.jl:142
[3] initialize_DCNetwork!(data::PowerFlows.PowerFlowData{…}, sys::System, bus_lookup::Dict{…}, reverse_bus_search_map::Dict{…}, removed_buses::Set{…}).....
.....

The zero-impedance reduction in PNM.jl was merging two distinct VSC terminal buses through an intermediate bus. PNM already supported irreducible buses, but the protection logic was checked against the original branch endpoints only. After an intermediate bus had already been merged, it was no longer recognized as belonging to a protected group and got reduced.

This PR ensures the VSC endpoint buses remain distinct through the zero-impedance reduction with the VSC control modes preserved so that PF.jl can map the converters to distinct reduced AC buses.

[github-actions]

Performance Results

Precompile Time

Main	This Branch	Delta
1.4 s	1.4 s	+3.3%

Execution Time

Cells show median (min–max) over 5 samples; delta compares medians.

Test	Main	This Branch	Delta
matpower_ACTIVSg2000_sys-Build Ybus	8.3 (8.2–9.3) ms	7.9 (7.7–9.4) ms	-3.8%
matpower_ACTIVSg2000_sys-Build PTDF	58.8 (58.0–60.6) ms	58.9 (58.1–59.4) ms	+0.2%
matpower_ACTIVSg2000_sys-Build LODF	120.6 (120.2–125.3) ms	119.0 (118.0–124.9) ms	-1.3%
matpower_ACTIVSg2000_sys-Build VirtualMODF	73.5 (72.9–73.9) ms	811.3 (810.8–812.1) ms	+1004.3%
matpower_ACTIVSg2000_sys-VirtualMODF Query 10 rows	0.5 (0.5–1.4) ms	0.6 (0.5–0.6) ms	+6.0%
matpower_ACTIVSg2000_sys-Radial network reduction	0.7 (0.7–1.0) ms	0.8 (0.8–1.1) ms	+15.1%
matpower_ACTIVSg2000_sys-Degree two network reduction	0.8 (0.8–0.8) ms	0.7 (0.7–0.8) ms	-6.5%
Base_Eastern_Interconnect_515GW-Build Ybus	496.3 (486.3–499.2) ms	428.1 (424.6–431.4) ms	-13.7%
Base_Eastern_Interconnect_515GW-Build VirtualPTDF	672.6 (668.4–708.6) ms	632.4 (627.6–638.2) ms	-6.0%
Base_Eastern_Interconnect_515GW-VirtualPTDF Query 10 rows	20.2 (19.4–20.7) ms	20.0 (19.7–20.1) ms	-0.8%
Base_Eastern_Interconnect_515GW-Build VirtualMODF	672.7 (668.4–675.5) ms	676.8 (672.3–682.0) ms	+0.6%
Base_Eastern_Interconnect_515GW-VirtualMODF Query 10 rows	24.6 (23.4–31.0) ms	23.6 (23.3–24.9) ms	-4.0%
Base_Eastern_Interconnect_515GW-Radial network reduction	29.0 (28.5–30.2) ms	29.4 (28.7–29.7) ms	+1.6%
Base_Eastern_Interconnect_515GW-Degree two network reduction	41.3 (41.1–42.1) ms	39.0 (38.9–39.9) ms	-5.5%

[m-bossart]

This is fixed in the psy6 line in #362. The handling of the zero impedance loops is in #368. We should port the tests included in those 2 PRs here. Other than that, just the one small fix. This PR and #368 should make the handling equivalent in main and psy6

[luke-kiernan]

I'll approve but I'd suggest adding a test case, or at least opening an issue to add one

[m-bossart]

I'll approve but I'd suggest adding a test case, or at least opening an issue to add one

There are tests in the PRs linked above that can be ported here

[mcllerena]

I'll approve but I'd suggest adding a test case, or at least opening an issue to add one

There are tests in the PRs linked above that can be ported here

I'll address the small fix and then port the test here before merging.

[m-bossart]

@mcllerena can you port the tests from #362 also

[mcllerena]

@mcllerena can you port the tests from #362 also

Yes, just pushed on the last commit.

[jd-lara]

This PR should be green in CI/CD to pass