Add B200 TP2 DSv4.1 Flash CPU offload / 新增 B200 TP2 DSv4.1 Flash CPU 卸载 - #3216

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feat/dsv41flash-b200-tp2-cpu-offload

Commits on Sep 17, 2026

feat: add B200 TP2 DSv4.1 Flash CPU-offload sweeps
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docs: link B200 TP2 sweep to PR 3216
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Commits on Sep 18, 2026

Merge origin/main into feat/dsv41flash-b200-tp2-cpu-offload

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dsv41flash agentic: TP2 memory caps for the B200 CPU-offload arm

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dsv41flash_fp4_b200_vllm_mtp.sh (8k1k): write the result JSON to the repo root

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test_dsv41flash_b200: expect the fixed-seq result dir at the container repo root

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dsv41flash_fp4_b200_vllm_mtp.sh (8k1k): cap TP2 graph capture at 256

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dsv41flash_fp4_b200_vllm_mtp.sh (8k1k): serve the matrix context, not 1M

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dsv41flash b200 tp2: floor --max-num-seqs at 16 and derive the eval context

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Merge remote-tracking branch 'origin/main' into feat/dsv41flash-b200-tp2-cpu-offload
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dsv41flash b200 tp2: give the accuracy evals memory to start

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Merge remote-tracking branch 'origin/main' into feat/dsv41flash-b200-tp2-cpu-offload
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dsv41flash b200 tp2: stage the accuracy-eval artifacts into the workspace

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Merge origin/main
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dsv41flash b200 tp2: keep the accuracy eval inside the CUDA-graph tier

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perf-changelog: use the dsv41flash-fp4-b200-vllm-dspark key for the TP2 eval entry

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Add B200 TP2 DSv4.1 Flash CPU offload / 新增 B200 TP2 DSv4.1 Flash CPU 卸载 - #3216

Add B200 TP2 DSv4.1 Flash CPU offload / 新增 B200 TP2 DSv4.1 Flash CPU 卸载#3216
functionstackx wants to merge 16 commits into
mainfrom
feat/dsv41flash-b200-tp2-cpu-offload

Commits on Sep 17, 2026

feat: add B200 TP2 DSv4.1 Flash CPU-offload sweeps

docs: link B200 TP2 sweep to PR 3216

Commits on Sep 18, 2026

Merge origin/main into feat/dsv41flash-b200-tp2-cpu-offload

dsv41flash agentic: TP2 memory caps for the B200 CPU-offload arm

dsv41flash_fp4_b200_vllm_mtp.sh (8k1k): write the result JSON to the repo root

test_dsv41flash_b200: expect the fixed-seq result dir at the container repo root

dsv41flash_fp4_b200_vllm_mtp.sh (8k1k): cap TP2 graph capture at 256

dsv41flash_fp4_b200_vllm_mtp.sh (8k1k): serve the matrix context, not 1M

dsv41flash b200 tp2: floor --max-num-seqs at 16 and derive the eval context

Merge remote-tracking branch 'origin/main' into feat/dsv41flash-b200-tp2-cpu-offload

dsv41flash b200 tp2: give the accuracy evals memory to start

Merge remote-tracking branch 'origin/main' into feat/dsv41flash-b200-tp2-cpu-offload

dsv41flash b200 tp2: stage the accuracy-eval artifacts into the workspace

Merge origin/main

dsv41flash b200 tp2: keep the accuracy eval inside the CUDA-graph tier

perf-changelog: use the dsv41flash-fp4-b200-vllm-dspark key for the TP2 eval entry