[FIX] RA: register allocator spill/reload closed loop via linear scan

[FeelTheBeats]

修复了两个问题，

1. 寄存器分配时，ScratchV没有简单的活跃变量分析，导致寄存器spill到栈上时，不知道什么时候lw。
2. 无脑使用flush在切换到新bb时，会将所有寄存器spill到栈上，这也是为什么发现了问题一
   附修改review
   RA_commit_architect_review.md
   ai建议的修改：
   pr-17.md

Implement liveness-driven spill→reload cycle in LinearScanAllocator:

• spill() now records reload positions for every future use of a spilled vreg; removes stale alloc_map entries after freeing a reg
• get_allocated_code() interleaves lw reloads before uses and sw spills after definitions
• New emit() one-shot entry point: intervals → allocate → codegen
• Fix compiler.py linear mode: process raw vreg instructions directly instead of re-scanning already-allocated physical registers
• Remove broken _flush_regs() at LABEL boundaries in greedy allocator that tore live ranges across labels and caused infinite loops

[watney1024]

lgtm

[Copilot]

Pull request overview

This PR updates ScratchV’s RISC-V register allocation pipeline to support a liveness-driven spill→reload cycle in the linear-scan allocator, adjusts compiler defaults/routing to use linear-scan directly, and adds stress/regression DSL tests targeting loop back-edges and high vreg pressure.

Changes:

• Add spill-store and reload insertion machinery to LinearScanAllocator, plus a new emit() one-shot entry point.
• Fix the “linear” compiler path to run linear-scan on raw virtual-register machine instructions (not on already-greedily-allocated code); set the default reg_alloc to "linear".
• Add stress tests for loop back-edge correctness and 32-vreg pressure; adjust assembler lw parsing to accept both offset(base) and base(offset) syntaxes.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
tests/stress/reg_pressure_loop.meta.json	New metadata for loop back-edge RA regression stress test.
tests/stress/reg_pressure_loop.dsl	New DSL program stressing loop header LABEL + accumulator across iterations.
tests/stress/reg_pressure_32.meta.json	New metadata for 32-vreg pressure spill/reload stress test.
tests/stress/reg_pressure_32.dsl	New DSL program creating peak liveness to force spilling.
scratchv/compiler.py	Default reg_alloc to linear; linear pipeline now runs linear-scan directly via emit().
scratchv/backend/riscv_encoder.py	Extend lw operand parsing to support alternate memory operand syntax; add parsing logic.
scratchv/backend/register_alloc.py	Remove greedy allocator’s LABEL-boundary _flush_regs() behavior.
scratchv/backend/regalloc_linear.py	Implement spill/reload scheduling and emit() entry point for linear-scan allocation.

Comments suppressed due to low confidence (2)

scratchv/backend/regalloc_linear.py:370

• Reload positions are only recorded for use_pos > current.start. For read-modify-write instructions where a vreg is both used and defined at the same instruction index (e.g. addi iv, iv, 1), use_pos can equal current.start, and the allocator will omit the reload that must happen before the instruction reads the old value.

            # Record reload at every future use of the spilled vreg
            for use_pos in spill_interval.uses:
                if use_pos > current.start:
                    self._reloads.setdefault(use_pos, []).append(
                        (spill_interval.vreg, slot))

scratchv/backend/regalloc_linear.py:382

• In the spill current interval path, the allocator unconditionally picks temp_reg = self.phys_regs[0] and assigns it to current.vreg even though the whole reason we’re in this branch is that all registers are occupied. This will overwrite whichever still-live vreg currently owns phys_regs[0] and produce incorrect code.

To spill the current interval safely, you need either (a) a dedicated scratch register that is never allocated, or (b) an explicit eviction step that stores some live register to its slot (before the instruction) and then reuses that freed register as the temporary.

        # Otherwise, spill the current interval
        slot = self._get_spill_slot(current.vreg)
        # Assign a temporary register for the definition instruction
        temp_reg = self.phys_regs[0]
        self.alloc_map[current.vreg] = temp_reg
        self._spilled.add(current.vreg)
        self.spill_code.setdefault(current.start, []).append(
            f"  sw {temp_reg}, {slot}(sp)  # spill {current.vreg}"
        )

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