perf(clr): Write AQL packets with non-temporal stores - #284
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Assigning a packet into its ring buffer slot pulls that slot's cache line in for ownership and dirties it, which buys nothing: the packet processor is the only other reader and it fetches the slot over the fabric anyway. Copy the 60 body bytes with non-temporal stores instead, so they land straight in the write-combining buffer, and keep publishing the header with the existing release store once an sfence has drained that buffer. The header dword stays out of the copy, so the slot holds the invalid header the packet processor left behind until the body has arrived. Covers kernel dispatch, barrier-AND and barrier-value packet submission.
saleelk
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chrispaquot,
mangupta and
rakesroy
as code owners
September 2, 2026 05:48
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Assigning a packet into its ring buffer slot pulls that slot's cache line in for ownership and dirties it, which buys nothing: the packet processor is the only other reader and it fetches the slot over the fabric anyway.
Copy the 60 body bytes with non-temporal stores instead, so they land straight in the write-combining buffer, and keep publishing the header with the existing release store once an sfence has drained that buffer. The header dword stays out of the copy, so the slot holds the invalid header the packet processor left behind until the body has arrived. Covers kernel dispatch, barrier-AND and barrier-value packet submission.
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