fix(clr): Order shared AQL ring publication on Intel hosts (AIRUNTIME-2291)

[saleelk]

Summary

Backport of the ordered AQL ring publication fix to release/rocm-rel-6.3.0.1.

When several VirtualGPUs multiplex onto one physical AQL ring, hsa_queue_add_write_index_screlease
advances the GPU-visible write index at reservation time. A later producer can therefore expose
its slot while an earlier producer is still writing its packet, and the in-order command processor
parks on that unwritten packet (or consumes torn state).

This splits slot reservation from publication:

• Each pooled hardware queue owns an AqlOrderedPublishState with shared reserve/commit indices.
• VirtualGPU::ReserveAqlSlots() allocates slots without making them visible to the GPU.
• VirtualGPU::CommitAqlSlots() stores the write index and rings the doorbell only once every
  older reservation has been published.

Gated to GenuineIntel hosts and controlled by the new DEBUG_CLR_ORDER_DOORBELL flag (default on);
other hosts keep the original HSA multi-producer path. Cooperative and CU-masked queues are not
shared between VirtualGPUs, so they keep the original path as well.

Publication order equals reservation order, so this cannot deadlock: the only blocking operations a
stream performs while holding a reservation (queue slot waits, completion signal waits) wait on
strictly older packets, which are published by definition.

Notes on this backport

The equivalent change is already on develop and release/rocm-rel-7.2. Differences here follow
from the older code base:

• No rocrctx wrapper layer, so HSA entry points are called directly.
• The state lives in Device::QueueInfo (there is no QueueExtras), and is looked up under
  vgpusAccess_, which is the lock that guards the queue pools on this branch.
• gpu_queue_ is bound exactly once in VirtualGPU::create(), so no set_gpu_queue() helper is
  needed to refresh the cached state.
• There is no batch dispatch path on this branch, so the reservation-index accessor used for batch
  pacing on 7.2 is omitted.

Test plan

• Each modified translation unit compiles clean (-fsyntax-only).
• Runtime validation on a 6.3.0.1 stack (the equivalent 7.2 change passed MultiThreadTest across
  all GPU_MAX_HW_QUEUES / DEBUG_CLR_ORDER_DOORBELL combinations).