TransferBench v1.70.00

CHANGELOG.md

@@ -3,6 +3,29 @@
 Documentation for TransferBench is available at
 [https://rocm.docs.amd.com/projects/TransferBench](https://rocm.docs.amd.com/projects/TransferBench).
 
+## v1.70.00
+### Added
+- Adding support for Tensor Data Mover (TDM)-based executor [T] on supported hardware (gfx1250, NVIDIA sm_90+ via TMA).
+  This provides an alternative data movement mechanism which utilizes async loads to shared memory / from shared memory
+- Added support for SWEEP_MIN_POW2 and SWEEP_MAX_POW2 to set sweep bounds when bytes to transfer is 0
+- Added new "tdmsweep" preset that sweeps TDM executor options (block size / LDS / block order / subExecs)
+- Added TB_SEND_USLEEP to insert a configurable microsecond delay after each socket SendData call (default: 0); useful for diagnosing small-message timing issues on sensitive clusters
+- Adding ppodId / vpodId printing to verbose mode
+- Added VALIDATE_ON_DEVICE to validate GPU destination (and source) memory via an on-device kernel instead of
+  copying back to the host. Expected values are pre-uploaded during preparation; only a mismatch count and the
+  first mismatch offset are returned. Takes precedence over VALIDATE_DIRECT for GPU destinations.
+### Modified
+- a2a, p2p, rings, poda2a, and podp2p presets now support the TDM executor
+- CPU NUMA nodes with 0 cores will now be hidden.  To re-enable, set TB_SHOW_ALL_NUMA=1
+- Switching to use of persistent threadpools to cut-down on thread creation overheads
+- Updating default GFX unroll on GFX1250 to 32
+- Improved socket communicator robustness (TCP_NODELAY, partial send/recv handling, MSG_NOSIGNAL)
+- Improved mismatch logging and smoketest fail reporting
+- Destination memory is now cleared after each iteration when ALWAYS_VALIDATE is enabled, so each iteration starts from a known-zero state
+### Fixed
+- Guard before ibv_free_device_list to avoid invalid free
+- Fix NIC to GPU proximity detection on systems with multiple PCIe domains
+
 ## v1.69.01
 ### Added
 - Added support for ABI change introduced in amd-smi 27.0.0 (ROCm 10.0)
@@ -21,7 +44,7 @@ Documentation for TransferBench is available at
   - Created a top level third-party/ folder for ibverbs related files. Will also harbor future external source which TransferBench depends
   - Created a separate minimal header IbvHeader.hpp for ib verbs structs and IbvDynLoad.hpp for dynamic loading and status report for ib verbs functionality.
   - Dynamic loading is a singleton and done once per process, and TransferBench header will probe in runtime if basic ibverbs function as well as dmabuf export is supported.
-  - Also got rid HAVE_DMABUF_SUPPORT macro. Got rid of redundant dependency check on hsa header and rocr binaries (they are mandatory for AMD platform) in build process. Similar to ibv, it now dynamically checks for hsa_amd_portable_export_dmabuf symbol as part of check kernel support, and returns dmabuf support in runtime.
+  - Also got rid of HAVE_DMABUF_SUPPORT macro. Got rid of redundant dependency check on hsa header and rocr binaries (they are mandatory for AMD platform) in build process. Similar to ibv, it now dynamically checks for hsa_amd_portable_export_dmabuf symbol as part of check kernel support, and returns dmabuf support in runtime.
 
 ## v1.68.00
 ### Fixed

CMakeLists.txt

@@ -103,8 +103,8 @@ set(ENV{ROCM_PATH} "${ROCM_PATH}")
 # TransferBench project definitions
 #==================================================================================================
 set(TRANSFERBENCH_VERSION_MAJOR 1)
-set(TRANSFERBENCH_VERSION_MINOR 69)
-set(TRANSFERBENCH_VERSION_PATCH_FALLBACK "01")
+set(TRANSFERBENCH_VERSION_MINOR 70)
+set(TRANSFERBENCH_VERSION_PATCH_FALLBACK "00")
 
 # Auto-compute patch from git: count commits since the last v<MAJOR>.<MINOR>.* tag.
 # Falls back to TRANSFERBENCH_VERSION_PATCH_FALLBACK when git is unavailable,

Makefile

@@ -6,7 +6,15 @@
 ROCM_PATH ?= /opt/rocm
 CUDA_PATH ?= /usr/local/cuda
 MPI_PATH  ?= /usr/local/openmpi
+# pip ROCm wheels ship bin/amdclang++ but often omit bin/amdllvm (which that stub execs).
+# Default to llvm/bin when bin/amdllvm is absent so HIP builds work without extra flags.
+ifeq ("$(shell test -e $(ROCM_PATH)/bin/amdllvm && echo found)", "found")
 HIPCC     ?= $(ROCM_PATH)/bin/amdclang++
+else ifeq ("$(shell test -e $(ROCM_PATH)/llvm/bin/amdclang++ && echo found)", "found")
+HIPCC     ?= $(ROCM_PATH)/llvm/bin/amdclang++
+else
+HIPCC     ?= $(ROCM_PATH)/bin/amdclang++
+endif
 NVCC      ?= $(CUDA_PATH)/bin/nvcc
 DEBUG     ?= 0
 

docs/conceptual/transferbench-data-validation.rst

@@ -142,6 +142,12 @@ environment variables or in a configuration file.
       - To compare GPU DST directly, set to ``1``. Supported on AMD hardware only and requires no host copy.
         To copy to host and compare, set to ``0``.
 
+    * - ``validateOnDevice``
+      - ``VALIDATE_ON_DEVICE``
+      - To compare GPU memory on the device via a kernel (expected values pre-uploaded during prep), set to ``1``.
+        Avoids the device-to-host copy; returns only a mismatch count and the first mismatch offset.
+        Takes precedence over ``validateDirect`` for GPU destinations.
+
     * - ``validateSource``
       - ``VALIDATE_SOURCE``
       - To validate the SRC memory right after it's initialized, set to ``1`` (optional early check).

docs/how to/use-transferbench.rst

@@ -10,11 +10,10 @@ Using TransferBench
 
 You can control the SRC and DST memory locations by indicating the memory type followed by the device index. TransferBench supports the following memory types:
 
-* Coarse-grained pinned host
+* Pinned host (default, closest-GPU, coherent, non-coherent, and uncached)
 * Unpinned host
-* Fine-grained host
-* Coarse-grained global device
-* Fine-grained global device
+* Coarse-grained, fine-grained, and uncached global device
+* Managed device
 * Null (for an empty transfer)
 
 In addition, you can determine the size of the transfer (number of bytes to copy) for the tests.
@@ -120,12 +119,20 @@ Here is the list of arguments used to specify transfers in the config file:
        | Memory locations are specified by one or more device characters or device index pairs.
        | Characters indicate memory type and are followed by device index (0-indexed).
        | Here are the characters and their respective memory locations:
-       | - C:    Pinned host memory       (on NUMA node, indexed from 0 to [NUMA nodes-1])
-       | - U:    Unpinned host memory     (on NUMA node, indexed from 0 to [NUMA nodes-1])
-       | - B:    Fine-grain host memory   (on NUMA node, indexed from 0 to [NUMA nodes-1])
-       | - G:    Global device memory     (on GPU device, indexed from 0 to [GPUs - 1])
-       | - F:    Fine-grain device memory (on GPU device, indexed from 0 to [GPUs - 1])
-       | - N:    Null memory              (index ignored)
+       | - C:    Pinned host memory              (on NUMA node, indexed from 0 to [NUMA nodes-1])
+       | - P:    Pinned host memory              (indexed by closest GPU, 0 to [GPUs-1])
+       | - B:    Coherent pinned host memory     (on NUMA node, indexed from 0 to [NUMA nodes-1])
+       | - D:    Non-coherent pinned host memory (on NUMA node, indexed from 0 to [NUMA nodes-1])
+       | - K:    Uncached pinned host memory     (on NUMA node, indexed from 0 to [NUMA nodes-1])
+       | - H:    Unpinned host memory            (on NUMA node, indexed from 0 to [NUMA nodes-1])
+       | - G:    Global device memory            (on GPU device, indexed from 0 to [GPUs-1])
+       | - F:    Fine-grain device memory        (on GPU device, indexed from 0 to [GPUs-1])
+       | - U:    Uncached device memory          (on GPU device, indexed from 0 to [GPUs-1])
+       | - M:    Managed device memory           (on GPU device, indexed from 0 to [GPUs-1])
+       | - N:    Null memory                     (index ignored)
+       |
+       | ``D`` in an executor position is the DMA executor. ``D`` in a SRC/DST position is
+       | non-coherent pinned host memory.
 
 Round brackets and arrows "->" can be included for human clarity, but will be ignored.
 Lines starting with # are ignored while lines starting with ## are echoed to the output.
@@ -140,6 +147,10 @@ Single DMA-executed transfer between GPU 0 and 1::
 
    1 1 (G0->D0->G1)
 
+Unpinned host to GPU 0 using the DMA executor (PCIe H2D)::
+
+   1 1 (H0->D0->G0)
+
 Copying 1Mb from GPU 0 to GPU 1 with 4 CUs, and 2Mb from GPU 1 to GPU 0 with 8 CUs::
 
    -2 (G0->G0->G1 4 1M) (G1->G1->G0 8 2M)

docs/reference/environment-variables.rst

@@ -139,6 +139,12 @@ Data and validation options
         On AMD hardware, the CPU can directly access GPU device memory, avoiding the need for a staging buffer. This feature is not supported on NVIDIA hardware.
       - ``0``
 
+    * - ``VALIDATE_ON_DEVICE``
+      - Specifies whether to validate GPU memory on the device instead of copying it back to the host. Set to ``1`` to validate on-device, ``0`` to copy to host and compare.
+
+        The expected values are pre-uploaded to the GPU during preparation, and a comparison kernel checks the destination in place, avoiding the device-to-host copy. Only a small result (mismatch count and first mismatch offset) is returned. Takes precedence over ``VALIDATE_DIRECT`` for GPU destinations; CPU destinations are always compared on the host.
+      - ``0``
+
     * - ``VALIDATE_SOURCE``
       - Specifies whether to validate the source immediately after preparation. Set to ``1`` to validate, ``0`` to skip.
 

src/client/Client.cpp

@@ -171,7 +171,7 @@ int main(int argc, char **argv)
     }
 
     // Run the specified numbers of bytes otherwise generate a range of values
-    for (size_t bytes = (1<<10); bytes <= (1<<29); bytes *= 2) {
+    for (size_t bytes = (1ULL<<ev.sweepMinPow2); bytes <= (1ULL<<ev.sweepMaxPow2); bytes *= 2) {
       size_t deltaBytes = std::max(1UL, bytes / ev.samplingFactor);
       size_t currBytes = (numBytesPerTransfer == 0) ? bytes : numBytesPerTransfer;
       do {