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[Engine] sm_52 build: leave the GP100-only weight-stationary down kernels empty below sm_53 - #4769

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Problem and result

The Maxwell (sm_52) recipe in docs/OLDER_GPUS.md does not build on current main (870aedd):

cmake -B build -G Ninja -DSTRATA_ENABLE_CUDA=ON -DSTRATA_EXPERIMENTAL_SM60=ON -DCMAKE_CUDA_ARCHITECTURES=52 \
      -DCMAKE_CUDA_COMPILER=<CUDA 12.9>/bin/nvcc
cmake --build build --target strata

stops in CMakeFiles/strata_mmq.dir/src/prefill/moe_ws_down.cu.o with 400 errors of the form

ptxas ... error : Feature 'f16 arithemetic and compare instructions' requires .target sm_53 or higher

moe_ws_down.cu (the GP100 weight-stationary down kernels) uses HFMA2, which ptxas accepts from sm_53. With this change the
build completes and the engine runs on a Tesla M40 (sm_52).

Related discussion

Refs #3218 (lower the architecture floor for Maxwell). The sm_52 floor itself is already in CMakeLists.txt (61ede87); this
only fixes the compile error that remains behind it. No scope change: setup.py still refuses Maxwell, as in c966d7a ("Maxwell gets a warning with
the build recipe, not an env switch"), and the closed Maxwell PRs (#3595, #3596) are not revived.

Approach

moe_ws.hpp says these kernels are for GP100 only, and ws::mode() returns 0 on any other card, so on sm_52 they are never
launched. The file is wrapped in #if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 530: the device pass is empty below sm_53,
the host pass (launch code, which prefill.cpp links against) is unchanged. 530 is the ISA limit ptxas reports, not a tuning
choice. I checked the other three moe_ws*.cu files: they compile unguarded for sm_52, so they are left alone.

Validation

Environment: Tesla M40 24 GB (sm_52), driver 580.159.03, Ubuntu 24.04 VM, gcc 13.3, CUDA 12.9.86, cmake 4.4.4, Strata main
870aedd plus this commit. Setup's own build of the engine was used for the run below; to let setup accept a 5.2 card I changed
sm60_card() locally. That change is not part of this PR.

Passed:

  • Before the change, the command above fails as described. Compiling each moe_ws*.cu for sm_52 on its own with the build's
    exact flags: moe_ws.cu, moe_ws_gu_iq2.cu, moe_ws_gu_iq3.cu compile; moe_ws_down.cu fails (400 ptxas errors).
  • After the change, setup's engine build for the M40 (-DSTRATA_EXPERIMENTAL_SM60=ON, arch 52) completes and links, with all four
    moe_ws*.cu objects rebuilt.
  • Device code unchanged elsewhere: compiling moe_ws_down.cu for sm_61, sm_75 and sm_86 with the build's flags, before and after, gives
    identical cuobjdump -sass instruction streams (12384 / 16160 / 16240 instructions).
  • Hardware run: Qwen3.8-Flash-Next Coder IQ1_M started on the M40 (about 23.6 of 24.5 GB VRAM) and answered two prompts. The capital of France
    was correct, and is_prime(n) came back as a complete, correct function. One run each, temperature 0; the 140-token code answer took 9.7 s
    end to end. That is a smoke test, not a benchmark under the community protocol.

Failed: nothing else observed. (Before the change: the build failure above.)

Not run:

  • sm_60 and sm_70 compile comparison, and any run on a P100/V100 (the one card the WS kernels are for). The guard leaves device code for
    sm_60+ unchanged by construction, and the SASS check above covers sm_61/75/86 only.
  • CUDA 13 release build, HIP, SYCL, the test suite, STRATA_BUILD_TESTS=ON.
  • Output quality on Maxwell beyond the two prompts above (the docs already say it is unchecked); other Maxwell cards or sm_50.

Limits

Maxwell is still only a hand build; this does not change setup.py or add a ready-made engine.

Prepared with Claude Code (AI-assisted): the diff is 8 lines in one file; the commands and results above were run on the machine described.

🤖 Generated with Claude Code

…nels empty below sm_53

The experimental build (-DSTRATA_EXPERIMENTAL_SM60=ON) compiles src/prefill/moe_ws_down.cu for every
architecture it targets. Its kernels use half-precision arithmetic (HFMA2), which ptxas accepts from sm_53,
so a Maxwell build (-DCMAKE_CUDA_ARCHITECTURES=52, the recipe in docs/OLDER_GPUS.md) stopped with
"Feature 'f16 arithemetic and compare instructions' requires .target sm_53 or higher".

The kernels only run on a GP100 (ws::mode() is 0 on any other card), so below sm_53 the device pass is now
left empty and the host code is unchanged. The device code for sm_60 and newer is identical.

Refs Niko1221#3218

Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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