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fix: declared _sm120 CUDA ops have no registered kernel - #77

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andrewwhitecdw:bugfix/bindings-f686cd64
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andrewwhitecdw wants to merge 1 commit into
NVlabs:mainfrom
andrewwhitecdw:bugfix/bindings-f686cd64

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This PR addresses the following issue in fouroversix/src/fouroversix/csrc/bindings.cpp: declared _sm120 CUDA ops have no registered kernel.

Changes

  • fouroversix/src/fouroversix/csrc/bindings.cpp: declared _sm120 CUDA ops have no registered kernel.

Details

--- a/fouroversix/src/fouroversix/csrc/bindings.cpp
+++ b/fouroversix/src/fouroversix/csrc/bindings.cpp
@@ -25,11 +25,8 @@ namespace fouroversix
     TORCH_LIBRARY(fouroversix, m)
     {
         m.def("quantize_to_fp4(Tensor x, bool is_nvfp4, bool is_rtn, bool is_rht, bool is_2d, bool is_transpose, int selection_rule, int rbits) -> (Tensor, Tensor, Tensor)");
         m.def("gemm_mxfp4mxfp4_accum_fp32_out_bf16_tnt(Tensor A, Tensor B, Tensor A_sf, Tensor B_sf, Tensor alpha) -> Tensor");
-        m.def("gemm_mxfp4mxfp4_accum_fp32_out_bf16_tnt_sm120(Tensor A, Tensor B, Tensor A_sf, Tensor B_sf, Tensor alpha) -> Tensor");
         m.def("gemm_nvfp4nvfp4_accum_fp32_out_bf16_tnt(Tensor A, Tensor B, Tensor A_sf, Tensor B_sf, Tensor alpha) -> Tensor");
-        m.def("gemm_nvfp4nvfp4_accum_fp32_out_bf16_tnt_sm120(Tensor A, Tensor B, Tensor A_sf, Tensor B_sf, Tensor alpha) -> Tensor");
         m.def("gemm_nvfp4nvfp4_accum_fp32_out_fp16_tnt(Tensor A, Tensor B, Tensor A_sf, Tensor B_sf, Tensor alpha) -> Tensor");
-        m.def("gemm_nvfp4nvfp4_accum_fp32_out_fp16_tnt_sm120(Tensor A, Tensor B, Tensor A_sf, Tensor B_sf, Tensor alpha) -> Tensor");
     }
 }

Tests

Let me know if you want tests added for this fix or not.

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