Add riscv fallback detection#261
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wcawijngaards
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Why
simdzone currently ships x86_64-specific SIMD kernels for Westmere and Haswell, plus a generic fallback parser. That fallback is the right conservative baseline for
riscv64until a dedicated RISC-V SIMD backend exists. However,src/isadetection.hstill checks raw x64 target macros directly, so forced-target validation on an x86_64 host can incorrectly enter the cpuid-based x64 detection path instead of the generic fallback path expected forriscv64.What changed
__riscvbranch tosrc/isadetection.hthat returnsDEFAULT, so RISC-V resolves to the existing fallback parser instead of inheriting x64 ISA detection.CMakeLists.txtto emit a clear configure-time status message when the target processor matchesriscv*, documenting that only the fallback kernel is built.README.mdto state that RISC-V and other non-x86_64 targets currently use the fallback kernel until a dedicated SIMD backend is added.Verification
cmake -S . -B build-native -G Ninja -DBUILD_TESTING=OFF -DBUILD_DOCUMENTATION=OFFcmake --build build-native --parallel 4riscv64cross build and install withdockcross/linux-riscv64:cmake -S /repo -B /tmp/simdzone-build -G Ninja -DCMAKE_BUILD_TYPE=Release -DCMAKE_SYSTEM_NAME=Linux -DCMAKE_SYSTEM_PROCESSOR=riscv64 -DCMAKE_C_COMPILER="$CC" -DCMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY -DBUILD_TESTING=OFFcmake --build /tmp/simdzone-build --parallel 4cmake --install /tmp/simdzone-build --prefix /tmp/simdzone-installzone_parse_stringconsumer against the installedlibzone.a:"$CC" -std=c99 -O2 -static -I/tmp/simdzone-install/include simdzone_smoke.c /tmp/simdzone-install/lib/libzone.a -o /tmp/simdzone_smoke.riscv64file /tmp/simdzone_smoke.riscv64readelf -h /tmp/simdzone_smoke.riscv64qemu-riscv64successfully:simdzone-ok count=1 ttl=3600 addr=192.0.2.1Notes
This is a conservative portability patch. It does not add RVV or any dedicated RISC-V SIMD implementation. The goal is to make
riscv64route cleanly to simdzone's existing fallback kernel and to keep x86_64-specific ISA detection from leaking into RISC-V validation.