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Merged
eyck merged 2 commits into from
Sep 23, 2026
Merged

Bugfix/act fixes #59

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95df664
changes to CSRs:
Sep 22, 2026
134c72e
bandaid fixes for gc floating point implementation:
Sep 22, 2026
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12 changes: 8 additions & 4 deletions src/iss/arch/riscv_hart_common.h
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Original file line number Diff line number Diff line change
Expand Up @@ -487,16 +487,20 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS

csr_rd_cb[mcycle] = MK_CSR_RD_CB(read_cycle);
csr_wr_cb[mcycle] = MK_CSR_WR_CB(write_cycle);
if(traits<BASE>::XLEN == 32)
if(traits<BASE>::XLEN == 32) {
csr_rd_cb[mcycleh] = MK_CSR_RD_CB(read_cycle);
if(traits<BASE>::XLEN == 32)
csr_wr_cb[mcycleh] = MK_CSR_WR_CB(write_cycle);
}
csr_rd_cb[minstret] = MK_CSR_RD_CB(read_instret);
csr_wr_cb[minstret] = MK_CSR_WR_CB(write_instret);
if(traits<BASE>::XLEN == 32)
if(traits<BASE>::XLEN == 32) {
csr_rd_cb[minstreth] = MK_CSR_RD_CB(read_instret);
if(traits<BASE>::XLEN == 32)
csr_wr_cb[minstreth] = MK_CSR_WR_CB(write_instret);
}
if(traits<BASE>::XLEN == 32) {
csr_rd_cb[mstatush] = MK_CSR_RD_CB(read_null);
csr_wr_cb[mstatush] = MK_CSR_WR_CB(write_null);
}
csr_rd_cb[mhartid] = MK_CSR_RD_CB(read_hartid);
};

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2 changes: 2 additions & 0 deletions src/iss/arch/riscv_hart_m_p.h
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Expand Up @@ -409,6 +409,8 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
case traits<BASE>::RV_CAUSE_ILLEGAL_INSTRUCTION:
#ifdef MTVAL_ILLEGAL_INFORMATIVE
this->csr[mtval] = (!this->has_compressed() || (tval & 0x3) == 3) ? tval : tval & 0xffff;
#else
this->csr[mtval] = 0;
#endif
break;
case traits<BASE>::RV_CAUSE_BREAKPOINT:
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2 changes: 2 additions & 0 deletions src/iss/arch/riscv_hart_msu_vp.h
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Expand Up @@ -631,6 +631,8 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_msu_vp<BASE, FEAT>
case traits<BASE>::RV_CAUSE_ILLEGAL_INSTRUCTION:
#ifdef MTVAL_ILLEGAL_INFORMATIVE
this->csr[utval | (new_priv << 8)] = (!this->has_compressed() || (tval & 0x3) == 3) ? tval : tval & 0xffff;
#else
this->csr[utval | (new_priv << 8)] = 0;
#endif
break;
case traits<BASE>::RV_CAUSE_BREAKPOINT:
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2 changes: 2 additions & 0 deletions src/iss/arch/riscv_hart_mu_p.h
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Expand Up @@ -506,6 +506,8 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
case traits<BASE>::RV_CAUSE_ILLEGAL_INSTRUCTION:
#ifdef MTVAL_ILLEGAL_INFORMATIVE
this->csr[utval | (new_priv << 8)] = (!this->has_compressed() || (tval & 0x3) == 3) ? tval : tval & 0xffff;
#else
this->csr[utval | (new_priv << 8)] = 0;
#endif
break;
case traits<BASE>::RV_CAUSE_BREAKPOINT:
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7 changes: 5 additions & 2 deletions src/vm/interp/vm_rv32gc.cpp
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Expand Up @@ -3742,7 +3742,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
{
*(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
*(F+rd) = NaNBox32((((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));

@eyck eyck Sep 23, 2026

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SInce this is generated code, Is this fixed in the CoreDSL description or generator??

@mag-de mag-de Sep 23, 2026

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No it is currently only fixed in the generated code, but @EAlexJ said he will fix the generator, as well.

}
break;
}// @suppress("No break at end of case")
Expand Down Expand Up @@ -4546,11 +4546,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
// used registers
auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]);
auto* FCSR = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::FCSR]);
// calculate next pc value
*NEXT_PC = *PC + 4;
// execute instruction
{
*(F+rd) = NaNBox64(f32tof64(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)));
uint32_t flags = fget_flags();

@eyck eyck Sep 23, 2026

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Same here: is it fixed in CoreDSL?

@mag-de mag-de Sep 23, 2026

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Same here, only fixed in the generated code.

*FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
}
break;
}// @suppress("No break at end of case")
Expand Down Expand Up @@ -4592,7 +4595,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
{
*(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
*(F+rd) = NaNBox64((((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
}
break;
}// @suppress("No break at end of case")
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7 changes: 5 additions & 2 deletions src/vm/interp/vm_rv64gc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5003,7 +5003,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
{
*(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
*(F+rd) = NaNBox32((((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
}
break;
}// @suppress("No break at end of case")
Expand Down Expand Up @@ -5835,11 +5835,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
// used registers
auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]);
auto* FCSR = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::FCSR]);
// calculate next pc value
*NEXT_PC = *PC + 4;
// execute instruction
{
*(F+rd) = NaNBox64(f32tof64(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)));
uint32_t flags = fget_flags();
*FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
}
break;
}// @suppress("No break at end of case")
Expand Down Expand Up @@ -5881,7 +5884,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
{
*(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
*(F+rd) = NaNBox64((((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
}
break;
}// @suppress("No break at end of case")
Expand Down
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