fix(privilege): implement non-H MPRV and xRET handling

[murdoa]

MPRV writes currently disappear, so M-mode loads and stores remain physical even with MPRV=1, MPP=S. For example, if satp maps VA 0x20000 to PA 0x30000, the load incorrectly reads physical 0x20000.

This implements MPRV for non-H cores with U support:

• Use MPP as effective data privilege when MPRV is set, leaving instruction fetch unchanged.
• Apply that privilege to translation and permission checks, preserving the accepted request's privilege/SUM/MXR through delayed walks.
• Include effective privilege and SUM/MXR in D-cache tags so warm hits cannot bypass changed permissions. No software fence is required.
• Legalize unsupported MPP values to M and keep MPRV zero when U is absent.
• Clear MPRV on returns below M. MRET to M preserves MPRV but resets MPP, so the next data access must use the new effective privilege.

Existing status aliases and the actual-mode DTLB flush policy are retained.

H support remains deferred

H-enabled cores retain their existing read-only-zero MPRV. This remains an architectural limitation. Supporting it requires coordinated MPP/MPV selection, separate fetch/data virtualization contexts and roots, VS SUM and host/VS MXR handling, HLV/HLVX/HSV overrides via SPVP, and correct VS xRET state/PC restoration. Guest-fetch translation is also outside this patch.

Testing

Compared against upstream 03df7bb:

• All 84 selected existing tests still pass, including the user-CSR and hypervisor suites.
• Of 45 new cases runnable on both versions, 40 fail on baseline; all 45 pass with the fix.
• Eight additional selector and delayed-walk cases pass with the new interface.

Coverage includes RV32/RV64 CSR behavior and RV64 Sv39 loads/stores with static and microcoded executors, with and without L1 caches. Tests exercise warm-cache permission changes, fetch isolation, and MRET-to-M behavior.

Changed production files retain the same nine analyzer diagnostics as baseline; new tests analyze cleanly. No full-suite or hardware validation was performed. The D-cache tags gain two permission bits; synthesis and FPGA timing have not been checked.